[VirtexII + DCM + newbie] problems with the clocksignals from DCM

hey, i have to use a DCM as i need multiple clocks now the problem is that
they should be de-asserted (not active) before some signal, so i need some
CE signal. i tried to solve it like this:

ddr_clkx2 <= ddr_clkx2_out and locked;

were locked is the lock signal from the DCM and the ddr_clkx2_out is a clock
output from the DCM and it should be 0 as long as locked is 0.
but when i use this trick it gives me the following warning when making the
bitfile (with bitgen):

WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0045 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.

so how should i implement it and what they mean with CE pin? well i know
what they mean but how should i implement it in VHDL for a VIRTEXII?

thanx in advance,

kind regards,

Yttrium

"Yttrium" wrote:

> ddr_clkx2 <= ddr_clkx2_out and locked;

That's BAD design, as the the tools are saying.  How bad?  If someone
working for me did that they'd be on the street faster than the PERIOD
constraint on the design.

Do a newsgroup/google/yahoo search for "gated clock" for more info.


> so how should i implement it and what they mean with CE pin? well i know
> what they mean but how should i implement it in VHDL for a VIRTEXII?

This is right out of the "Language Templates" found under the "Edit" menu:

-- D Flip Flop with Clock Enable
--     CLK: in STD_LOGIC;
--     ENABLE: in STD_LOGIC;
--     DIN: in STD_LOGIC;
--     DOUT: out STD_LOGIC;

process (CLK)
    begin
        if (CLK'event and CLK='1') then
    if (ENABLE='1') then
             DOUT <= DIN;
            end if;
        end if;
end process;



-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"

One possibility is to use the BUFGMUX primitive to switch between idle and
active.  I haven't used it for this purpose yet myself, so be *sure* to read
the Libraries Guide entry on the BUFGMUX in the online SW Manuals.  There
may be a design issue if one of the two clocks in the BUFGMUX is inactive,
so do your homework before just trying it out.

"Yttrium" <Yttrium@pandora.be> wrote in message
news:7Erxb.46705$Wr1.1566834@phobos.telenet-ops.be...
> hey, i have to use a DCM as i need multiple clocks now the problem is that
> they should be de-asserted (not active) before some signal, so i need some
> CE signal. i tried to solve it like this:
>
> ddr_clkx2 <= ddr_clkx2_out and locked;
>
> were locked is the lock signal from the DCM and the ddr_clkx2_out is a
clock
> output from the DCM and it should be 0 as long as locked is 0.
> but when i use this trick it gives me the following warning when making
the
> bitfile (with bitgen):
>
> WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0045 is
sourced
> by a combinatorial pin. This is not good design practice. Use the CE pin
to
> control the loading of data into the flip-flop.
>
> so how should i implement it and what they mean with CE pin? well i know
> what they mean but how should i implement it in VHDL for a VIRTEXII?
>
> thanx in advance,
>
> kind regards,
>
> Yttrium
>
>

Martin Euredjian wrote:

> "Yttrium" wrote:
> 
> 
>>ddr_clkx2 <= ddr_clkx2_out and locked;
> 
> 
> That's BAD design, as the the tools are saying.  

Agreed, it is not good FPGA design.

But the crazy thing is that Xilinx has the ability to do this relatively 
safely... but they don't seem to push it very hard and the tools don't 
automatically use it for you.  Check out the BUFGCE in the V2 and S3 
devices.

Not portable, but usable.

    Marc

If you know what you are doing, sure.  Like most things, there's a rule and
then reasons to break it.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



"Marc Randolph" <mrand@my-deja.com> wrote in message
news:dotxb.3054$NK3.1109@newssvr24.news.prodigy.com...
> Martin Euredjian wrote:
>
> > "Yttrium" wrote:
> >
> >
> >>ddr_clkx2 <= ddr_clkx2_out and locked;
> >
> >
> > That's BAD design, as the the tools are saying.
>
> Agreed, it is not good FPGA design.
>
> But the crazy thing is that Xilinx has the ability to do this relatively
> safely... but they don't seem to push it very hard and the tools don't
> automatically use it for you.  Check out the BUFGCE in the V2 and S3
> devices.
>
> Not portable, but usable.
>
>     Marc
>

you're right it is a bad design, but like i mentioned in my subject, i'm
just a newbie getting to know VHDL and FPGA's...

thanx for the tips ... found some good info (not only concering this
problem) ... so thanx for your answer!

kind regards

y


"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:sSsxb.26673$9P7.1856@newssvr29.news.prodigy.com...
> "Yttrium" wrote:
>
> > ddr_clkx2 <= ddr_clkx2_out and locked;
>
> That's BAD design, as the the tools are saying.  How bad?  If someone
> working for me did that they'd be on the street faster than the PERIOD
> constraint on the design.
>
> Do a newsgroup/google/yahoo search for "gated clock" for more info.
>
>
> > so how should i implement it and what they mean with CE pin? well i know
> > what they mean but how should i implement it in VHDL for a VIRTEXII?
>
> This is right out of the "Language Templates" found under the "Edit" menu:
>
> -- D Flip Flop with Clock Enable
> --     CLK: in STD_LOGIC;
> --     ENABLE: in STD_LOGIC;
> --     DIN: in STD_LOGIC;
> --     DOUT: out STD_LOGIC;
>
> process (CLK)
>     begin
>         if (CLK'event and CLK='1') then
>     if (ENABLE='1') then
>              DOUT <= DIN;
>             end if;
>         end if;
> end process;
>
>
>
> -- 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_"  =  "martineu"
>
>

i'll check it out ... thanx for the tip

kind regards,

y

"Marc Randolph" <mrand@my-deja.com> wrote in message
news:dotxb.3054$NK3.1109@newssvr24.news.prodigy.com...
> Martin Euredjian wrote:
>
> > "Yttrium" wrote:
> >
> >
> >>ddr_clkx2 <= ddr_clkx2_out and locked;
> >
> >
> > That's BAD design, as the the tools are saying.
>
> Agreed, it is not good FPGA design.
>
> But the crazy thing is that Xilinx has the ability to do this relatively
> safely... but they don't seem to push it very hard and the tools don't
> automatically use it for you.  Check out the BUFGCE in the V2 and S3
> devices.
>
> Not portable, but usable.
>
>     Marc
>

"Yttrium" wrote:

> you're right it is a bad design, but like i mentioned in my subject, i'm
> just a newbie getting to know VHDL and FPGA's...

To be sure it went across correctly, I wasn't criticizing you
personally...just wanted to stress that this isn't a good idea in general.

Think hardware design without an FPGA.  Most of the same rules apply.

A clock mux on a V2 will switch between clocks cleanly.  That's a resource
you can use.  However, you need to have the right reasons to do so.  If it's
simply to keep a FF from latching an input, it's probably safe to say that
this would be a bad idea.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"

"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:dlPxb.27551$ZS.24820@newssvr29.news.prodigy.com...
> "Yttrium" wrote:
>
> > you're right it is a bad design, but like i mentioned in my subject, i'm
> > just a newbie getting to know VHDL and FPGA's...
>
> To be sure it went across correctly, I wasn't criticizing you
> personally...just wanted to stress that this isn't a good idea in general.

Yes, i know ;-) ... just wanted to stress that fact hehe ...

>
> Think hardware design without an FPGA.  Most of the same rules apply.
>

indeed indeed, i think the main problem was getting used to the fact that
VHDL is a programming language but it designs hardware. so you tend to think
to much in a software way, but i'm learning not to :-)

> A clock mux on a V2 will switch between clocks cleanly.  That's a resource
> you can use.  However, you need to have the right reasons to do so.  If
it's
> simply to keep a FF from latching an input, it's probably safe to say that
> this would be a bad idea.
>
>

i couldn't use the solution with the ce FF because the system clock is on
the same clock as on of the output clock signals from the DCM so that would
have divided the frequency by 2. but i looked at the BUFGCE component and
that seems to have solved the problem (warning) but i'm still looking if the
BUFGMUX. but for now the BUFGCE seems to be the solution ...

thanx, for the comments and help,

kind regards,

Yttrium

> -- 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_"  =  "martineu"
>
>

"Yttrium" wrote:

> indeed indeed, i think the main problem was getting used to the fact that
> VHDL is a programming language but it designs hardware.

Well, technically it is an HDL ... "Hardware Description Language".  The
trick is to not think "sofware" at all and think that you are describing
hardware constructs.  That alone should keep you honest.

> i couldn't use the solution with the ce FF because the system clock is on
> the same clock as on of the output clock signals from the DCM so that
would
> have divided the frequency by 2.


I'm not sure I follow this without having more context in terms of what the
design is attempting to do.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"