Problem to extend Xilinx GSRD Design

Hi i'm using the Xilinx GSRD design.

Now i try to connect a simple IP core to the reference design.
The problem is that i can not connect my IP to the OPB or PLB bus. The 2 
PLB Bus controllers supports only 1 Master and 1 Slave and they are 
alread connected.

The connection over the OPB does not work because they use a DCR2OPB 
bridge. May be the way over the DCR is a solution? How can i manage this 
connection. Are there some examples?

Eric

tester wrote:
> Hi i'm using the Xilinx GSRD design.
> 
> Now i try to connect a simple IP core to the reference design.
> The problem is that i can not connect my IP to the OPB or PLB bus. The 2 
> PLB Bus controllers supports only 1 Master and 1 Slave and they are 
> alread connected.
> 
> The connection over the OPB does not work because they use a DCR2OPB 
> bridge. May be the way over the DCR is a solution? How can i manage this 
> connection. Are there some examples?

You should switch over to the new MPMC2 based design which supports
what you are looking for  http://www.xilinx.com/mpmc2

Ed McGettigan
--
Xilinx Inc.

Eric,

I am in the same boat. The workaround I found was to replace one of the
plb_m1s1 cores with the standard plb_v34. So far this seems to have worked
but I haven't finished the testing yet...

MPMC2 approach Ed mentioned would probably be a more natural approach but I
didn't want to mess with replacing the memory controller as I wasn't sure it
was fully compatible with the GSRD design...


/Mikhail



"tester" <test@test.de> wrote in message news:e808lk$dae$1@nntp.aioe.org...
> Hi i'm using the Xilinx GSRD design.
>
> Now i try to connect a simple IP core to the reference design.
> The problem is that i can not connect my IP to the OPB or PLB bus. The 2
> PLB Bus controllers supports only 1 Master and 1 Slave and they are
> alread connected.
>
> The connection over the OPB does not work because they use a DCR2OPB
> bridge. May be the way over the DCR is a solution? How can i manage this
> connection. Are there some examples?
>
> Eric

MM wrote:
> Eric,
> 
> I am in the same boat. The workaround I found was to replace one of the
> plb_m1s1 cores with the standard plb_v34. So far this seems to have worked
> but I haven't finished the testing yet...
> 
> MPMC2 approach Ed mentioned would probably be a more natural approach but I
> didn't want to mess with replacing the memory controller as I wasn't sure it
> was fully compatible with the GSRD design...

The latest (June 1st) release of the MPMC2 code base includes the
equivalent of the original GSRD design using the new MPMC2 controller.

We haven't had time to update the GSRD page to note this release yet.
You want to start with project/ml403_ddr_idpoc_100mhz_gsrd.zip file.  The
"_idpoc_" part denotes that the design uses the following interfaces:

   i = ISPLB       (connects to PPC405 I-side PLB)
   d = DSPLB       (connects to PPC405 D-side PLB)
   p = PLB master  (connects to general PLB arbiter)
   o = OPB master  (connects to general OPB arbiter)
   c = CDMAC       (connects to the TEMAC)

You should really upgrade to the new code base there is a lot more that
you can do with this version.

Ed McGettigan
--
Xilinx Inc.

Thanks a lot Ed! It would be nice if you at least put a notice on the GSRD
page. I've been waiting for this new release for quite a while... Anyways, I
would be still interested to know whether the fix I applied to the original
design would be expected to work?

Thanks,
/Mikhail



"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message
news:e81ac2$8q33@cliff.xsj.xilinx.com...
> MM wrote:
> > Eric,
> >
> > I am in the same boat. The workaround I found was to replace one of the
> > plb_m1s1 cores with the standard plb_v34. So far this seems to have
worked
> > but I haven't finished the testing yet...
> >
> > MPMC2 approach Ed mentioned would probably be a more natural approach
but I
> > didn't want to mess with replacing the memory controller as I wasn't
sure it
> > was fully compatible with the GSRD design...
>
> The latest (June 1st) release of the MPMC2 code base includes the
> equivalent of the original GSRD design using the new MPMC2 controller.
>
> We haven't had time to update the GSRD page to note this release yet.
> You want to start with project/ml403_ddr_idpoc_100mhz_gsrd.zip file.  The
> "_idpoc_" part denotes that the design uses the following interfaces:
>
>    i = ISPLB       (connects to PPC405 I-side PLB)
>    d = DSPLB       (connects to PPC405 D-side PLB)
>    p = PLB master  (connects to general PLB arbiter)
>    o = OPB master  (connects to general OPB arbiter)
>    c = CDMAC       (connects to the TEMAC)
>
> You should really upgrade to the new code base there is a lot more that
> you can do with this version.
>
> Ed McGettigan
> --
> Xilinx Inc.

MM wrote:
> Thanks a lot Ed! It would be nice if you at least put a notice on the GSRD
> page. I've been waiting for this new release for quite a while... Anyways, I
> would be still interested to know whether the fix I applied to the original
> design would be expected to work?

If the workaround is what you described as "replace[ed] one of the
plb_m1s1 cores with the standard plb_v34" then it probably still
works. However, with the latest GSRD with MPMC2 design this isn't
needed at all as you can build a MPMC2 core with bridges to PLB and OPB
instead.  This should result in a smaller and faster design than what
you describe.

I agree that it would be a good thing to note on the GSRD landing page.
I will ping the appropriate people on this and see if we can get it
added.

Ed McGettigan
--
Xilinx Inc.

"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message
news:e81pbr$90u1@cliff.xsj.xilinx.com...
> If the workaround is what you described as "replace[ed] one of the
> plb_m1s1 cores with the standard plb_v34" then it probably still
> works.

Yes, that's what I did. I was just a little worried that the 1 master/1
slave restriction resulted from some MPMC design limitation...

> However, with the latest GSRD with MPMC2 design this isn't
> needed at all as you can build a MPMC2 core with bridges to PLB and OPB
> instead.  This should result in a smaller and faster design than what
> you describe.

This is all great and I am definitely going to switch to the new design; my
only problem at the moment is that I had to modify the ll_temac core to
support RGMII mode and now I will have to figure out whether I have to do it
all again or I can reuse my modified ll_temac core... Have you done anything
to the ll_temac?

Also, at some point in the near future I will need to have two TEMACs
connected to the same PPC... Could you tell me if this can be done in the
new MPMC2 based design?

Thanks,
/Mikhail

MM wrote:
> 
> This is all great and I am definitely going to switch to the new design; my
> only problem at the moment is that I had to modify the ll_temac core to
> support RGMII mode and now I will have to figure out whether I have to do it
> all again or I can reuse my modified ll_temac core... Have you done anything
> to the ll_temac?
> 
> Also, at some point in the near future I will need to have two TEMACs
> connected to the same PPC... Could you tell me if this can be done in the
> new MPMC2 based design?
> 

The current design was released with a GMII interface.  We do plan
on releasing a design with the RGMII interface, but there are other
higher priority items on the plate right now.  Since this is just
the interface between the LL_TEMAC core and the IOs, you should be
able to just use the same code that you have right now.

With MPMC2 you can have 2 or 3 or 4 LL_TEMACs in the design as the
controller core now supports up to 8 ports of any type.  There are
hooks in the current LL_TEMAC design to support the dual mode, but
we haven't released a pre-built design with this yet.

Ed McGettigan
--
Xilinx Inc.

I did some download and try the new MPMC2. Since I have Virtex4FX12
MiniModule I tried the MiniModule reference design
(v4fx12mm_ddr_idpp_100mhz.zip) before I tried to modify the GSRD2
reference design, which is bult for ML403
(ml403_ddr_idpoc_100mhz_gsrd.zip). The v4fx12mm reference design IS NOT
WORKING. I could not get anything from UART, which is like being blind
for me. I contacted support and Glenn Baxter said to me that the design
is thorougly tested. The design cannot work because there is at least
one error in ddr_mem_test.c - UartBaseAdr is assigned with no value. I
spend some more time on the design but still I couldn't get anything
from UART (must be some HW error). Some more mails to mr. Baxter did'n
help, so I quit trying and dedicate my time to my cores. I still wait
for the solution.
By the way: Glenn said that Linux support for GSRD2 is probably to be
expected at the end of June. Is that true? Will we finally get the
"real thing"?

Cheers,

Guru

Guru wrote:
> I did some download and try the new MPMC2. Since I have Virtex4FX12
> MiniModule I tried the MiniModule reference design
> (v4fx12mm_ddr_idpp_100mhz.zip) before I tried to modify the GSRD2
> reference design, which is bult for ML403
> (ml403_ddr_idpoc_100mhz_gsrd.zip). The v4fx12mm reference design IS NOT
> WORKING.
<snip>
Out of curiousity: did you EVER have a GSRD implementation working on
the MiniModule?  I actually emailed Xilinx a while ago asking if this
reference design would work on the MiniModule, and I was told that it
would not due to several technical reasons (that were all enumerated at
the time, and made sense to me, though I don't have them in front of me
right now).  So, I'd be curious to hear if you had the original GSRD
working, and if you do in fact get the GSRD2 working.

Regards,
John O.
www.jrobot.net