Symon schrieb:> "Peter Alfke" <alfke@sbcglobal.net> wrote in message > news:1151994135.380653.322220@h44g2000cwa.googlegroups.com... > >>I am so happy to have removed the mystery from metastability. I do not >>want to get chaos back in. >>It is the simplicity of the CMOS latch structure that causes >>metastability to be so well-behaved and incapable of any oscillation. >>Nobody has ever reported oscillation in CMOS latches (but well in TTL >>structures that are more complex). Hurray for simplicity... >>I think the pen analogy is valid... >>Peter Alfke >>===================== > > Hi Peter, > I agree with you, the pen example is rather good. Over the years, people > like Xilinx have been making the tip of the pen sharper and sharper. > On to chaos: I don't think a system needs oscillation of each component > comprising the system in order to be chaotic. The resultant system changing > state is the chaotic thing, rather than the FF oscillating. For example :- > http://en.wikipedia.org/wiki/Logistic_mapYou use different meanings of the word oscillation. Peter meant this with oscillation: http://en.wikipedia.org/wiki/Oscillation_%28mathematics%29 "In mathematics, oscillation is the behaviour of some sequences, or a function, that does not converge, but also does not diverge to +∞ or -∞; that is, oscillation is the failure to have a limit." With that definition the population example clearly oscillates for all values of r larger than 3.57. The article you cited state the opposite: "At r = 3.57 (approximately) is the onset of chaos. We can no longer see any oscillations." This comes from a definition of oscillation like this http://en.wikipedia.org/wiki/Oscillation "Oscillation is the periodic variation,...". I guess that is what you mean with oscillation. Anyway, you need negative feedback for chaos in a system and the CMOS latch does not have any.> Also, what matters is the sensitivity to initial conditions. Again see the > previous example.Yes, but in the model. Chaos and noise are different things. If you flip the coin in an identical way (not possible, but thats beside the point) it will always show the same behaviour in the abscense of noise. There is a threshold value. Below the threshold it will flip one way, above it will flip the other way. A chaotic system would show some complicated pattern close to the threshold without noise. The pencil experiment with added noise will look very similar to that, but that is not what chaos theory is about.> In conclusion, I think an individual CMOS FF given a single metastable clock > event doesn't comprise a chaotic system, but you can make a chaotic system > with several of them, no trouble.Sure. You can build a CPU out of them an compute the logistic map ;-) Kolja Sulimma
Chaos in FF metastability
Started by ●July 3, 2006
Reply by ●July 4, 20062006-07-04
Reply by ●July 4, 20062006-07-04
Peter Alfke wrote:> I am so happy to have removed the mystery from metastability. I do not > want to get chaos back in. > It is the simplicity of the CMOS latch structure that causes > metastability to be so well-behaved and incapable of any oscillation. > Nobody has ever reported oscillation in CMOS latches (but well in TTL > structures that are more complex). Hurray for simplicity... > I think the pen analogy is valid...What feature about the CMOS latch makes it impossible to oscillate? My understanding is that there are two nodes with logic driving them to opposite polarities. If the FF is driven into metastability the two nodes can be driven to the same state which due to the logic, is unstable. since there is a delay from the input to the output of each node, it should be possible for each node to drive the other to the opposite state, then both nodes will be in the other state and drive the other node to the original state, etc. What prevents this in CMOS logic?
Reply by ●July 4, 20062006-07-04
"rickman" <spamgoeshere4@yahoo.com> wrote:>What feature about the CMOS latch makes it impossible to oscillate? My >understanding is that there are two nodes with logic driving them to >opposite polarities. If the FF is driven into metastability the two >nodes can be driven to the same state which due to the logic, is >unstable. since there is a delay from the input to the output of each >node, it should be possible for each node to drive the other to the >opposite state, then both nodes will be in the other state and drive >the other node to the original state, etc. What prevents this in CMOS >logic?Disclaimer: naive understanding exposed herein, without benefit of clear understanding of control theory :-) Roughly, I think it's because the CMOS latch circuit has only 2 gain stages in its loop, and both of them have delays that are dominated by an RC effect (first-order) and, by comparison, its time delays are negligible. So the whole thing is quite highly damped. By contrast, TTL latch circuits often had rather more gain stages, I think. If you simply cross-couple a pair of bipolar transistors you get an embarrassingly slow circuit; TTL used all kinds of tricks to make it faster - remember that NPN transistors were cheap, but just about any other kind of component on TTL was troublesome to make. If you use an ordinary digital simulator to model a two-inverter feedback loop, and give each inverter a pure time delay, it's easy to make the thing oscillate by prodding it appropriately. But if the two inverting gain stages have a first-order RC-type lag that swamps their propagation delay, an analog simulation will show the thing settling monotonically after any disturbance from its metastable "balance point". I'd be *very* pleased to hear any experts explaining, in a way that I can understand both mathematically and intuitively, a more rigorous version. Control theory always pushed the limits of my mathematical competence, and as the math wiring in my head shows an approximately exponential decay with time, it needs to be pretty simple these days if I'm going to follow it... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●July 4, 20062006-07-04
On 3 Jul 2006 23:22:15 -0700, "Peter Alfke" <alfke@sbcglobal.net> wrote:>I am so happy to have removed the mystery from metastability. I do not >want to get chaos back in. >It is the simplicity of the CMOS latch structure that causes >metastability to be so well-behaved and incapable of any oscillation. >Nobody has ever reported oscillation in CMOS latches (but well in TTL >structures that are more complex). Hurray for simplicity... >I think the pen analogy is valid...TTL flipflops were symmetric master-slave architectures with lots of delay in the positive feedback path. If they did get into serious oscillation, the saturation of various stages effectively reduced positive-feedback loop gain. LSTTL was notorious for metastable oscillations, with hundreds of cycles, lasting microseconds, observed. An FM radio would now and then click when placed near a big LSTTL system. CMOS transmission-gate latches don't have this combination of symmetry and delay, so don't oscillate; the balanced pen is a good analogy. I've seen ecl flops ring once before resolving, but I don't think they sustain an oscillation either. John
Reply by ●July 4, 20062006-07-04
>I think the pen analogy is valid...I use a ball rolling over a speed-bump. It's naturally only one dimensional. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●July 5, 20062006-07-05
On Tue, 04 Jul 2006 18:14:21 -0500, hmurray@suespammers.org (Hal Murray) wrote:> >>I think the pen analogy is valid... > >I use a ball rolling over a speed-bump. It's naturally only >one dimensional.I'm not convinced by these dynamics analogies. These are just unstable systems in an enery maxima, where a slight perturbation leads to a more stable, lower energy, configuration. In normal (my normal, anyway) usage of the term 'metastable', what's meant is an asychronous circuit with feedback, in which more than one input changes 'simultaneously', leading to oscillation because of a hazard. In practical circuits, the oscillation is damped and decays. Ok, in some practical circuits there may not be enough energy involved to actually switch a transistor and it may hold in an intermediate state for a significant time, but this is just a detail. Using this to describe general 'metastability' seems to me to be ignoring the big picture. Evan
Reply by ●July 5, 20062006-07-05
On Wed, 05 Jul 2006 10:40:41 +0100, Evan Lavelle <eml@nospam.co.uk> wrote:>Using this to >describe general 'metastability' seems to me to be ignoring the big >picture.Before you complain, I'm sure you're all quite capable of explaining the big picture as well... :)
Reply by ●July 5, 20062006-07-05
"Evan Lavelle" <eml@nospam.co.uk> wrote in message news:l20na2hjs05c14rrvmt5dcdrh2opl50i74@4ax.com...> On Tue, 04 Jul 2006 18:14:21 -0500, hmurray@suespammers.org (Hal > Murray) wrote: > >> >>>I think the pen analogy is valid... >> >>I use a ball rolling over a speed-bump. It's naturally only >>one dimensional. > > I'm not convinced by these dynamics analogies. These are just unstable > systems in an enery maxima, where a slight perturbation leads to a > more stable, lower energy, configuration. > > In normal (my normal, anyway) usage of the term 'metastable', what's > meant is an asychronous circuit with feedback, in which more than one > input changes 'simultaneously', leading to oscillation because of a > hazard. In practical circuits, the oscillation is damped and decays. >Hi Evan, Not all metastablility manifests itself as an oscillation. e.g. CMOS FFs. In fact a metastable FF doesn't necessarily have to have oscillation or even a 'funny' output voltage. (Imagine a circuit which has a funny output voltage followed by a comparator with large hysteresis) All it must have is an indeterminate clock to output delay. I think you're wise to be unconvinced by dynamics analogies. I agree you need different analogies for different FF technologies, but the pen/speed bump ones are good for what's inside CMOS FFs. Probably! :-) Cheers, Syms. p.s. Just in case you haven't seen it, there some stuff on Philip's website which may be of interest. http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm
Reply by ●July 5, 20062006-07-05
>>I use a ball rolling over a speed-bump. It's naturally only >>one dimensional. > >I'm not convinced by these dynamics analogies. These are just unstable >systems in an enery maxima, where a slight perturbation leads to a >more stable, lower energy, configuration.I like the ball because the key idea, energy, is so obvious. It takes energy to change states. You get in trouble when you don't have enough. If the ball is rolling too slowly it won't get over the bump. If the setup/hold times are not met (or the clock pulse isn't clean) you get a runt pulse which doesn't have enough energy to change the state of the FF.>In normal (my normal, anyway) usage of the term 'metastable', what's >meant is an asychronous circuit with feedback, in which more than one >input changes 'simultaneously', leading to oscillation because of a >hazard. In practical circuits, the oscillation is damped and decays.It doesn't take two inputs. You can get metastability with a simple runt pulse into a R/S FF. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●July 5, 20062006-07-05
On Wed, 05 Jul 2006 10:41:00 -0500, hmurray@suespammers.org (Hal Murray) wrote:>>In normal (my normal, anyway) usage of the term 'metastable', what's >>meant is an asychronous circuit with feedback, in which more than one >>input changes 'simultaneously', leading to oscillation because of a >>hazard. In practical circuits, the oscillation is damped and decays. > >It doesn't take two inputs. You can get metastability with a simple >runt pulse into a R/S FF.These are analog circuits, so you can always find a way to set a gate input such that an output is neither '0' nor '1'. Is that metastability? This is just semantics, but I would say not; it's just another (uninteresting) way to get an invalid output. Philip Freidin's article (the link posted by Symon) appears to talk exclusively about the multi-input synchronisation version of metastability, which is what I understand the word to mean. Evan
