Chaos in FF metastability

Let's go back to the word origin and the definition:
meta (from the Greek) means "between", stable (from Latin) means, well,
stable...

In electronics it is used to describe a circuit with positive feedback
that is unconditionally stable at either of two levels (High and Low)
but can also be "metastable" in the balanced condition.
In the stable conditions, a small disturbance (epsilon) will cause the
state to revert to the previous stable state, but in the metastable
state any disturbance will cause the circuit to go to the nearest
stable state.
That's what is also true in the analogy of the pen standing on its tip.
Try it!

Peter Alfke, Xilinx
==================
Evan Lavelle wrote:
> On Wed, 05 Jul 2006 10:41:00 -0500, hmurray@suespammers.org (Hal
> Murray) wrote:
>
> >>In normal (my normal, anyway) usage of the term 'metastable', what's
> >>meant is an asychronous circuit with feedback, in which more than one
> >>input changes 'simultaneously', leading to oscillation because of a
> >>hazard. In practical circuits, the oscillation is damped and decays.
> >
> >It doesn't take two inputs.  You can get metastability with a simple
> >runt pulse into a R/S FF.
>
> These are analog circuits, so you can always find a way to set a gate
> input such that an output is neither '0' nor '1'. Is that
> metastability? This is just semantics, but I would say not; it's just
> another (uninteresting) way to get an invalid output.
> Philip Freidin's article (the link posted by Symon) appears to talk
> exclusively about the multi-input synchronisation version of
> metastability, which is what I understand the word to mean.
> 
> Evan

On 5 Jul 2006 13:56:50 +0200, "Symon" <symon_brewer@hotmail.com>
wrote:

>Hi Evan,
>Not all metastablility manifests itself as an oscillation. e.g. CMOS FFs. In 

Sure, I agree; I thought I'd covered that with my comment on the
switching energy and the damping.

Having said that, I like to think of metastability in terms of hazards
in K-maps. If you do the wrong thing to the inputs, and the K-map says
that the output oscillates (or you have one switching input and a
hazard), then you've got metastability. What actually happens in a
practical circuit will depend on how it's constructed. 

Evan

Peter Alfke wrote:
> Let's go back to the word origin and the definition:
> meta (from the Greek) means "between", stable (from Latin) means, well,
> stable...
>
> In electronics it is used to describe a circuit with positive feedback
> that is unconditionally stable at either of two levels (High and Low)
> but can also be "metastable" in the balanced condition.
> In the stable conditions, a small disturbance (epsilon) will cause the
> state to revert to the previous stable state, but in the metastable
> state any disturbance will cause the circuit to go to the nearest
> stable state.
> That's what is also true in the analogy of the pen standing on its tip.
> Try it!

But you have not responded as to why the FF can not oscillate.  The FF
is more than just a penl standing on end or a ball on a hill.  A FF is
a dynamic system with feedback and delays.  My schooling taught me that
with the right combination of delay and gain (or the wrong combination)
it can oscillate.  What makes these FFs different?

The pen analogy is not a lot different from the pendulum.  Yet a
pendulum can be chaotic!  I think the pen is only good as a first order
approximation.  For this sort of issue, the analogy requires further
scrutiny.

Evan Lavelle wrote:

> On 5 Jul 2006 13:56:50 +0200, "Symon" <symon_brewer@hotmail.com>
> wrote:
> 
> 
>>Hi Evan,
>>Not all metastablility manifests itself as an oscillation. e.g. CMOS FFs. In 
> 
> 
> Sure, I agree; I thought I'd covered that with my comment on the
> switching energy and the damping.
> 
> Having said that, I like to think of metastability in terms of hazards
> in K-maps. If you do the wrong thing to the inputs, and the K-map says
> that the output oscillates (or you have one switching input and a
> hazard), then you've got metastability. What actually happens in a
> practical circuit will depend on how it's constructed. 
> 
> Evan

That's different than metastability.  You are talking about dynamic 
hazards (race conditions). Given a sequence of inputs and a circuit with 
a dynamic hazard, the circuit will respond exactly the same way every 
time the same input (levels and timing) is applied.  Although the 
operation may not be what the designer intended due to the dynamic 
hazards, it is still a deterministic system.  Metastability is a very 
specific condition where the outcome is not deterministic.  It occurs in 
a system with positive feedback when the input changes occur in such a 
way (with a very specific timing) that the circuit ends up balancing in 
a state that is neither '1' nor '0'.

Ray Andraka wrote:
> >
> That's different than metastability.  You are talking about dynamic
> hazards (race conditions). Given a sequence of inputs and a circuit with
> a dynamic hazard, the circuit will respond exactly the same way every
> time the same input (levels and timing) is applied.  Although the
> operation may not be what the designer intended due to the dynamic
> hazards, it is still a deterministic system.  Metastability is a very
> specific condition where the outcome is not deterministic.  It occurs in
> a system with positive feedback when the input changes occur in such a
> way (with a very specific timing) that the circuit ends up balancing in
> a state that is neither '1' nor '0'.

Let me continue the story:
And that balanced state may even appear like a legitimate 1 or 0 on the
circuit output, but the internal falling back into the stable 1 or 0
may (or may not) create an output transition that occurs at a
non-deterministic time after the clock edge that started the operation.
It is this unknown (and unknowable) delay that can create havoc in an
otherwise synchronous system.

Peter Alfke, Xilinx

rickman wrote:
> Peter Alfke wrote:
> 
>>Let's go back to the word origin and the definition:
>>meta (from the Greek) means "between", stable (from Latin) means, well,
>>stable...
>>
>>In electronics it is used to describe a circuit with positive feedback
>>that is unconditionally stable at either of two levels (High and Low)
>>but can also be "metastable" in the balanced condition.
>>In the stable conditions, a small disturbance (epsilon) will cause the
>>state to revert to the previous stable state, but in the metastable
>>state any disturbance will cause the circuit to go to the nearest
>>stable state.
>>That's what is also true in the analogy of the pen standing on its tip.
>>Try it!
> 
> 
> But you have not responded as to why the FF can not oscillate.  The FF
> is more than just a penl standing on end or a ball on a hill.  A FF is
> a dynamic system with feedback and delays.  My schooling taught me that
> with the right combination of delay and gain (or the wrong combination)
> it can oscillate.  What makes these FFs different?
> 
> The pen analogy is not a lot different from the pendulum.  Yet a
> pendulum can be chaotic!  I think the pen is only good as a first order
> approximation.  For this sort of issue, the analogy requires further
> scrutiny.

Put this into a Spice pgm, and try it.

In fact, (good) spice should be able to show the settling-time-extension
effects of metastability quite well. It would need carefull sweep
of the drive voltage, at the instant the clock does the hand-over.

The FF I am used to, is Analog transmission gates, around single
CMOS INV/OR gates - two forming the regenerative latch.

These simple 'unbuffered' CMOS structures have finite analog gain, even 
at their peak, in the linear region. (unlike TTL ones )

To build an oscillator, you must hold them in the linear region (DC),
and provide phase shift at some other frequency, where the loop
gain is still over unity.

Yes, there are parasitics all around, but the FF lacks the linear-bias
mechanism, so it cannot sustain oscillation.

I am sure some would look pretty knarly, as they settled, and may not
be monotonic, but these times will be very short.
During this settling time, they will also be at their most sensitive to
crosstalk effects.

-jg

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
news:uocla2t93lffghk9705huv57gviq6gega9@4ax.com...
> "rickman" <spamgoeshere4@yahoo.com> wrote:
>
>>What feature about the CMOS latch makes it impossible to oscillate?  My
>>understanding is that there are two nodes with logic driving them to
>>opposite polarities.  If the FF is driven into metastability the two
>>nodes can be driven to the same state which due to the logic, is
>>unstable.  since there is a delay from the input to the output of each
>>node, it should be possible for each node to drive the other to  the
>>opposite state, then  both nodes will be in the other state and drive
>>the other node to the original state, etc.  What prevents this in CMOS
>>logic?
>
> Disclaimer: naive understanding exposed herein, without benefit
> of clear understanding of control theory :-)
>
> Roughly, I think it's because the CMOS latch circuit has only 2 gain
> stages in its loop, and both of them have delays that are dominated
> by an RC effect (first-order) and, by comparison, its time delays are
> negligible.  So the whole thing is quite highly damped. By contrast,
> TTL latch circuits often had rather more gain stages, I think.  If you
> simply cross-couple a pair of bipolar transistors you get an
> embarrassingly slow circuit; TTL used all kinds of tricks to make
> it faster - remember that NPN transistors were cheap, but just
> about any other kind of component on TTL was troublesome
> to make.
>
> If you use an ordinary digital simulator to model a two-inverter
> feedback loop, and give each inverter a pure time delay, it's
> easy to make the thing oscillate  by prodding it appropriately.
> But if the two inverting gain stages have a first-order RC-type
> lag that swamps their propagation delay, an analog simulation
> will show the thing settling monotonically after any disturbance from
> its metastable "balance point".
>

If you have studied Op-amps, which have negative feedback instead
of positive feedback, you are probably familiar with the bode plot.
http://en.wikipedia.org/wiki/Bode_plot

The key to stabilizing the op-amp is to insure that the feedback
gain (open loop gain/closed loop gain) drops below unity before
the additional phase shift reaches 180 degrees.  For instance,
take a look at the Open Loop Gain and Phase plots on page 7:
http://cache.national.com/ds/LM/LMH6624.pdf
In this case, the phase shift reaches 180 degrees at about 250
MHz while the gain is still 10dB.  If you use this op-amp in
a unity gain application, it will oscillate (hence the
recommendation to use it for gains of 10 or greater).

A similar analysis applies to flip-flops.  The main difference
is that here the feedback is positive (-360 degrees) and so
latching to one side or the other is a stable state.  If
you get an additional -360 degrees of phase shift before
the open loop gain reaches zero, the device can oscillate
at that freqency if stimulated properly.

2 gain stages with single pole RC roll-off will have a maximum
additional phase shift of -180 degrees.  Cascading 4 or more
gain stages will usually ensure that the phase shift exceeds
-360 degrees before unity gain is reached due to the presence
of higher order poles & wire delays.

Daniel Lang

Daniel Lang <invalid@invalid.caltech.edu> wrote:

>If you have studied Op-amps, which have negative feedback instead
>of positive feedback, you are probably familiar with the bode plot.

Yup.  Studied, used, taught about :-)

>The key to stabilizing the op-amp is to insure that the feedback
>gain (open loop gain/closed loop gain) drops below unity before
>the additional phase shift reaches 180 degrees.

Indeed.  That's a nice simple explanation that's often missing
from the textbooks.

>A similar analysis applies to flip-flops.  The main difference
>is that here the feedback is positive (-360 degrees) and so
>latching to one side or the other is a stable state.  If
>you get an additional -360 degrees of phase shift before
>the open loop gain reaches zero, the device can oscillate
>at that freqency if stimulated properly.

OK, thanks for that insight - the (rather obvious) point I'd
missed was that you need an extra *360deg* of phase
shift to get the thing to oscillate, not 180deg.

>2 gain stages with single pole RC roll-off will have a maximum
>additional phase shift of -180 degrees.  Cascading 4 or more
>gain stages will usually ensure that the phase shift exceeds
>-360 degrees before unity gain is reached due to the presence
>of higher order poles & wire delays.

OK.  Thanks for the nice and appropriate description.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Jim Granville wrote:
> rickman wrote:
> > But you have not responded as to why the FF can not oscillate.  The FF
> > is more than just a penl standing on end or a ball on a hill.  A FF is
> > a dynamic system with feedback and delays.  My schooling taught me that
> > with the right combination of delay and gain (or the wrong combination)
> > it can oscillate.  What makes these FFs different?
> >
> > The pen analogy is not a lot different from the pendulum.  Yet a
> > pendulum can be chaotic!  I think the pen is only good as a first order
> > approximation.  For this sort of issue, the analogy requires further
> > scrutiny.
>
> Put this into a Spice pgm, and try it.

Two reasons why I can't... 1) I don't have Spice  2)  I don't have
"this".


> In fact, (good) spice should be able to show the settling-time-extension
> effects of metastability quite well. It would need carefull sweep
> of the drive voltage, at the instant the clock does the hand-over.

I am sure it can, but several posts here claim that CMOS FFs can't
oscillate and I am asking how people know this is a true fact.
Obviously simulating it or hooking up a test circuit can't prove it
won't oscillate.  That can only prove it won't oscillate under those
conditions.


> The FF I am used to, is Analog transmission gates, around single
> CMOS INV/OR gates - two forming the regenerative latch.
>
> These simple 'unbuffered' CMOS structures have finite analog gain, even
> at their peak, in the linear region. (unlike TTL ones )

Why do you call this "unbuffered"?  Don't the gates create gain and
delay?  The more I think about this, the more I am starting to believe
that a FF is capable of chotic behavior.

> To build an oscillator, you must hold them in the linear region (DC),
> and provide phase shift at some other frequency, where the loop
> gain is still over unity.

I don't think that is true.  The TTL FFs (or coupled inverters) that
oscillate don't remain in the linear region.  They peg the rails and
the delays cause them to peg to the other rail when the feedback takes
effect.

> Yes, there are parasitics all around, but the FF lacks the linear-bias
> mechanism, so it cannot sustain oscillation.
>
> I am sure some would look pretty knarly, as they settled, and may not
> be monotonic, but these times will be very short.
> During this settling time, they will also be at their most sensitive to
> crosstalk effects.

rickman wrote:
> Jim Granville wrote:
> 
>>rickman wrote:
>>
>>>But you have not responded as to why the FF can not oscillate.  The FF
>>>is more than just a penl standing on end or a ball on a hill.  A FF is
>>>a dynamic system with feedback and delays.  My schooling taught me that
>>>with the right combination of delay and gain (or the wrong combination)
>>>it can oscillate.  What makes these FFs different?
>>>
>>>The pen analogy is not a lot different from the pendulum.  Yet a
>>>pendulum can be chaotic!  I think the pen is only good as a first order
>>>approximation.  For this sort of issue, the analogy requires further
>>>scrutiny.
>>
>>Put this into a Spice pgm, and try it.
> 
> 
> Two reasons why I can't... 1) I don't have Spice  2)  I don't have
> "this".
> 
> 
> 
>>In fact, (good) spice should be able to show the settling-time-extension
>>effects of metastability quite well. It would need carefull sweep
>>of the drive voltage, at the instant the clock does the hand-over.
> 
> 
> I am sure it can, but several posts here claim that CMOS FFs can't
> oscillate and I am asking how people know this is a true fact.
> Obviously simulating it or hooking up a test circuit can't prove it
> won't oscillate.  That can only prove it won't oscillate under those
> conditions.
Hi  rickman,

I find spice very good, for getting a 'feel' of how a circuit behaves,
and you can add parasitics as you wish.

Of course, every instance is different, but spice gives a good data-point.

It also depends on what you mean by 'oscillate' :
If you mean settle-whilst-ringing, or non-monotonic settling,
then I'd call that very probable : but best modeled as an
extended settling time, in the digital domain.
( which is what metastability is )

If you mean run forever at XX MHz, then that becomes improbable to
the point that any device so poorly designed, would be culled.

If you want a historical/physical sort of proof, look at the
old 2 transistor cross-coupled multivibrator.
Same regenerative scheme, at the high frequency realm.

Transistors have more gain than a single FET, but this circuit
does not oscillate at the 4 x Tpd rate - it does not have
sufficent gain/phase to do so.

> 
>>The FF I am used to, is Analog transmission gates, around single
>>CMOS INV/OR gates - two forming the regenerative latch.
>>
>>These simple 'unbuffered' CMOS structures have finite analog gain, even
>>at their peak, in the linear region. (unlike TTL ones )
> 
> 
> Why do you call this "unbuffered"?  Don't the gates create gain and
> delay?  

"unbuffered' refers to the simplest 2 fet INV / 4 fet OR/NAND.
Std CMOS logic is usually buffered ( chain of 3 gates )
- look a 74AHCU04 data - this is a unbuffered inverter, used
for Xtal oscillators, and a similar structure is found in most
micocontrollers.

> The more I think about this, the more I am starting to believe
> that a FF is capable of chotic behavior.

Then we agree ?

How practical it is to get a number of FF's into this zone, with
usefull 'yield', is another question.

-jg