Chaos in FF metastability

Here comes some basic stuff. Excuse me if you find it boring.

Most metastable problems are cused by input set-up time violations on
classical edge-triggered flip-flops. Such flip-flops consist of a
master latch and a slave latch.

When the clock is Low, the D input drives the master latch, which does
not have any feedback during that time. The slave latch is isolated
from the master, and retains the previous data through its slave-latch
feedback.

When the clock is High, the master latch is isolated form the D input,
retaining data by means of its master-latch feedback. The slave latch
then has no feedback, but is directly driven by the output of the
master latch.

Metastability occurs when the input data happened to change exactly to
a specific "bad" level, just at the moment when the clock rises. At
that moment the master latch is being decoupled from the D input, and
the master-latch feedback is being activated. That is the (only) moment
when a (rising-edge triggered) flip-flop can go metastable. Only the
master latch is responsible for metastability.

To analyze the behavior, we look at the innards of the master latch: it
consists of two cascaded simple inverter stages, each with a p-channel
pull-up transistor and an n-challel pull-down transistor (nothing but
these four transistors with very short connections between them) plus a
clock-controlled pass transistor feeding the output back to the input.
That's all, none of all that TTL junk that caused those metastable
problems decades ago.

What happens when the master latch exits the metastable state?
We can model that by (conceptually or really) driving the input of the
double-inverter to an input voltage that is identical with the output
voltage, which means both inverters are in their linear range. Any
two-stage (non-hysteresis) non-inverting amplifier has such an
operating point where Vin = Vout. To go metastable, we have to hit
exactly (or almost exactly) that point.
Now we activate the pass transistor that connects Vout to Vin. Nothing
happens momentarily, since, by definition, there is no voltage
difference.
But very soon a voltage difference will develop and will drive the
output either to the positive or the negative rail.
The debate in this thread has been whether that recovery from
metastability is monotonic, or can involve oscillation. I claim it is
monotonic since the phase response of the circuit loop is dominated by
the RC of pass transitor impedance times input capacitance.
Perhaps somebody with a more recent education can take it from here.

If the structure is any more complicated, involving additional
transistors or lengthy interconnects, all bets are off, and the circuit
may have poor metastable behavior. But we are not interested in such a
bad circuit..
Peter Alfke

Peter Alfke wrote:
<Snip>> We can model that by (conceptually or really) driving the input 
of the
> double-inverter to an input voltage that is identical with the output
> voltage, which means both inverters are in their linear range. Any
> two-stage (non-hysteresis) non-inverting amplifier has such an
> operating point where Vin = Vout. 
 > To go metastable, we have to hit
> exactly (or almost exactly) that point.
> Now we activate the pass transistor that connects Vout to Vin. Nothing
> happens momentarily, since, by definition, there is no voltage
> difference.
> But very soon a voltage difference will develop and will drive the
> output either to the positive or the negative rail.
> The debate in this thread has been whether that recovery from
> metastability is monotonic, or can involve oscillation. I claim it is
> monotonic since the phase response of the circuit loop is dominated by
> the RC of pass transitor impedance times input capacitance.
> Perhaps somebody with a more recent education can take it from here.

Yes: I would call it 'behavioural monotonic'.

Parasitic ringing and coupling effects may add to this, but it will
not oscillate in the classic sense.

The biggest disturbance source is likely to be the capacitance of the
pass switch, as the IP signal has to be changing at the clock instant,
in order to hit the metastable jackpot.

-jg

Peter Alfke wrote:
> Here comes some basic stuff. Excuse me if you find it boring.
>
> Most metastable problems are cused by input set-up time violations on
> classical edge-triggered flip-flops. Such flip-flops consist of a
> master latch and a slave latch.
>
> When the clock is Low, the D input drives the master latch, which does
> not have any feedback during that time. The slave latch is isolated
> from the master, and retains the previous data through its slave-latch
> feedback.
>
> When the clock is High, the master latch is isolated form the D input,
> retaining data by means of its master-latch feedback. The slave latch
> then has no feedback, but is directly driven by the output of the
> master latch.
>
> Metastability occurs when the input data happened to change exactly to
> a specific "bad" level, just at the moment when the clock rises. At
> that moment the master latch is being decoupled from the D input, and
> the master-latch feedback is being activated. That is the (only) moment
> when a (rising-edge triggered) flip-flop can go metastable. Only the
> master latch is responsible for metastability.
>
> To analyze the behavior, we look at the innards of the master latch: it
> consists of two cascaded simple inverter stages, each with a p-channel
> pull-up transistor and an n-challel pull-down transistor (nothing but
> these four transistors with very short connections between them) plus a
> clock-controlled pass transistor feeding the output back to the input.
> That's all, none of all that TTL junk that caused those metastable
> problems decades ago.
>
> What happens when the master latch exits the metastable state?
> We can model that by (conceptually or really) driving the input of the
> double-inverter to an input voltage that is identical with the output
> voltage, which means both inverters are in their linear range. Any
> two-stage (non-hysteresis) non-inverting amplifier has such an
> operating point where Vin = Vout. To go metastable, we have to hit
> exactly (or almost exactly) that point.
> Now we activate the pass transistor that connects Vout to Vin. Nothing
> happens momentarily, since, by definition, there is no voltage
> difference.
> But very soon a voltage difference will develop and will drive the
> output either to the positive or the negative rail.

AH!  We have the first condition for chaotic behaviour, sensitivity to
initial conditions...  When the input is near the balance point, the
slightest difference will determine whether the output goes positive or
negative.  That is a very significant aspect of the circuit.


> The debate in this thread has been whether that recovery from
> metastability is monotonic, or can involve oscillation. I claim it is
> monotonic since the phase response of the circuit loop is dominated by
> the RC of pass transitor impedance times input capacitance.
> Perhaps somebody with a more recent education can take it from here.

I think there is more to it than just oscillation.  Chaotic behavior
does not require the same things.  Once the input to the inverter has
varied just a bit the output will move in the opposite direction.  But
there is a delay (which is mostly from the RC it appears).  If the
input then moves (from noise or parasitic feedback or any other reason)
in the opposite direction as its initial movement, the output will
start to swing in the other direction.  Now we have two larger
amplitude swings at different times chasing each other around the loop.
 Given all the various parasitics and delays, I don't see why this
could not create oscillation and possibly chaotic behavior.  Obviously
it doesn't, but I don't think we still know why as yet.


> If the structure is any more complicated, involving additional
> transistors or lengthy interconnects, all bets are off, and the circuit
> may have poor metastable behavior. But we are not interested in such a
> bad circuit..

I don't know what is so different about the TTL FF because no one has
explained why it is soooo "bad".

rickman wrote:
> > I don't know what is so different about the TTL FF because no one has
> explained why it is soooo "bad".

A TTL-fli-flop uses far more transistors than a CMOS flip-flop does.
There are no pass gates in TTL. Also, bipolar TTL cicuits combined
relatively slow transistors with relatively fast metal-interconnect. In
CMOS it's the other way round: extremely fast transistors, but
relatively slow capacitively loaded interconnects.

If I simplify my explanation and claim that the phase delay through the
two cascaded inverters is insignificant compared to the phase delay
through the pass transistor, (loaded by the input capacitance,) then my
explanation becomes very clear: the response must be monotonic.
It's like the old thumb rule: You can always prevent a feedback system
from oscillating, if you make one of the low-pass time constants
dominant, i.e. much slower than all the others.

Somebody with a more recent education and stronger background in linear
circuit analysis and feedback theory (someone who can analyze the
response of a PLL) can surely give a more quantitative answer.
Don't leave me alone. The solution is staring you in the face !

Peter Alfke

rickman wrote:
> I don't know what is so different about the TTL FF because no one has
> explained why it is soooo "bad".

My Philips 74AHC1G79 data shows the internal circuit, of a modern CMOS 
FF (no reset). Philips 74AUP1G175 shows a variant with RESET.
My Fairchild 74AC74 datasheet, shows an older FF (TTL style) with 10 
nand gates.
-jg

Diagrams in data sheets are almost always meant to give a logical 
understanding of how the device functions, not an exact indication of how it 
is built or works.

Marco
________________________
Marc Reinig
UCO/Lick Observatory
Laboratory for Adaptive Optics

"Jim Granville" <no.spam@designtools.co.nz> wrote in message 
news:44aec339$1@clear.net.nz...
> rickman wrote:
>> I don't know what is so different about the TTL FF because no one has
>> explained why it is soooo "bad".
>
> My Philips 74AHC1G79 data shows the internal circuit, of a modern CMOS FF 
> (no reset). Philips 74AUP1G175 shows a variant with RESET.
> My Fairchild 74AC74 datasheet, shows an older FF (TTL style) with 10 nand 
> gates.
> -jg
> 

Thanks Jim.
The CMOS design is really as simple as shown, each inverter-triangle
really consisting of 2 transistors, and the square transfer gate being
a single transistor.
Each of the many NAND gates in TTL, however, is each a complex
multi-transistor structure.
No wonder is has enough loop time to oscillate.

Nostalgia:
The 7474 dual flip-flop stems from 1969. Its improved brother, the
Fairchild 9024, was introduced a few weeks before I joined Fairchild in
CA in the summer of 1969, as part of the seemingly insane program to
introduce one new IC per week on a double-page spread in EETimes. We
continued for a whole year, even when it sometimes became a mad
scramble. Those were the days before the straight-laced types from
Motorola took over the company, and before the French then ruined it
"for good". Then NSC took over, and now Fairchild is re-born.
7474 in 2006, is this a fast-paced industry?...
Peter Alfke

Jim Granville wrote:
> rickman wrote:
> > I don't know what is so different about the TTL FF because no one has
> > explained why it is soooo "bad".
>
> My Philips 74AHC1G79 data shows the internal circuit, of a modern CMOS
> FF (no reset). Philips 74AUP1G175 shows a variant with RESET.
> My Fairchild 74AC74 datasheet, shows an older FF (TTL style) with 10
> nand gates.
> -jg

Marco, not at the simple level we are talking about here.
Lying about the physical structure, or using sophisticated abstractions
at these low levels, would become self-defeating. Remember, those
schematics are there to minimize support questions...
I remember explaining "ones-catching flip-flops" in those days..
Peter Alfke

==========
Marc Reinig wrote:
> Diagrams in data sheets are almost always meant to give a logical
> understanding of how the device functions, not an exact indication of how it
> is built or works.
> 
> Marco
>

>AH!  We have the first condition for chaotic behaviour, sensitivity to
>initial conditions...  When the input is near the balance point, the
>slightest difference will determine whether the output goes positive or
>negative.  That is a very significant aspect of the circuit.

When I think of chaos, I think of hard to predict systems.  The classic
example is the earth's weather pattern.  We think we can analyze the
local details but we can't predict anything long term.

In the case of metastability, the system eventually stabilizes at
a 1 or 0.  That's two possible states rather than zillions.

Is it called "chaotic" if I can't predict when it will stabilize?

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Hal Murray wrote:
> >AH!  We have the first condition for chaotic behaviour, sensitivity to
> >initial conditions...  When the input is near the balance point, the
> >slightest difference will determine whether the output goes positive or
> >negative.  That is a very significant aspect of the circuit.
>
> When I think of chaos, I think of hard to predict systems.  The classic
> example is the earth's weather pattern.  We think we can analyze the
> local details but we can't predict anything long term.
>
> In the case of metastability, the system eventually stabilizes at
> a 1 or 0.  That's two possible states rather than zillions.
>
> Is it called "chaotic" if I can't predict when it will stabilize?

I am looking for the possiblity that a FF Can be chaotic.  I don't know
the formal definition of chaotic so I don't know how to tell if a FF
can behave chaotically or not.  At least I didn't when I started this
thread.  I think that a chaotic system has to not settle and it seems
clear at this point that the CMOS FF using pass transistors (if
designed properly) will always settle.

I was considering the possibility that if you balanced the FF close
enough to the threshold that it may behave chaotically not too
different from a damped, driven pendulum.  I was not aware of this, but
if you release the pendulum of your grandfather clock close enough to
the threshold it will not settle into a period and it will not stop.
Rather it will continue to swing in a non-periodic way.  Another
chaotic system is a dripping faucet.  The dripping faucet was actually
studied by some of the pioneers in chaos theory.

Since the CMOS FF appears to be overdamped, it will not behave
chaotically.  But if the RC of the pass transistor does not adequately
compensate for the gain of the inverters, it has a chance at chaos.
But peroidic oscillations are not chaos either.  So even then it may
just be an oscillator.