did you connect Vccaux? (2.5V) Aurash blisca wrote:>for reading the device ID how should the PROGRAM pin be ? > >thank you all >(i'm still spending hours and days trying to do it,no way....no activity on >TDI or TDO) > > >here ,once ,more the things that i did: > >i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not >easy to test it (soldering wires on a bga as i do is even worse ...)but it >looks >that it should be enough for the core,correct???or i need to > >i connected in 7 points the 3.3VCCO(A2,B2,B12 , A13,G12,N1,M2) and the >ground in 3 >points(A1,J1,N12) > >i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level >amplifier) > >I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same >result..... > >I left M0 and M2 open,and them are high,M1 tied to ground,this for choosing >boundary scan mode > >using the debug chain utility i verified that the signals are working but i >noticed that there is no movement on TMS,and of course on TDO > >there is something else missing? > >Thank you to everyone in the group that will help me or just will read this > >Diego > > > > > >-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
Re: can't read device ID xcv200....what about the PROGRAM pin
Started by ●July 3, 2006
Reply by ●July 3, 20062006-07-03
blisca schrieb:> for reading the device ID how should the PROGRAM pin be ? > > thank you all > (i'm still spending hours and days trying to do it,no way....no activity on > TDI or TDO)Hi I have succesfully soldered wires to Virtex 2000 BGA and the proto did work prog_b needs to have an pullup to logic high level xilinx datasheet says it has internal pullup but on Virtex family JTAG config does not work without external pullup, that is the JTAG chain is accessible but configuratio fails. minimal connections are GND VCCINT VCCIO in the bank that supply JTAG PROG_B pullup JTAG pins thats all! if those connections are ok the FPGA should get configured over JTAG Antti http://antti-brain.com
Reply by ●July 3, 20062006-07-03
you can get away (sometimes) by not connecting all the VCCIO (for the unused banks, if these paticular banks don't have configuration pins belonging to them) but I'll strongly advise to connect all Vccint ans Vccaux Aurash blisca wrote:>for reading the device ID how should the PROGRAM pin be ? > >thank you all >(i'm still spending hours and days trying to do it,no way....no activity on >TDI or TDO) > > >here ,once ,more the things that i did: > >i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not >easy to test it (soldering wires on a bga as i do is even worse ...)but it >looks >that it should be enough for the core,correct???or i need to > >i connected in 7 points the 3.3VCCO(A2,B2,B12 , A13,G12,N1,M2) and the >ground in 3 >points(A1,J1,N12) > >i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level >amplifier) > >I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same >result..... > >I left M0 and M2 open,and them are high,M1 tied to ground,this for choosing >boundary scan mode > >using the debug chain utility i verified that the signals are working but i >noticed that there is no movement on TMS,and of course on TDO > >there is something else missing? > >Thank you to everyone in the group that will help me or just will read this > >Diego > > > > > >-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
Reply by ●July 3, 20062006-07-03
for reading the device ID how should the PROGRAM pin be ? thank you all (i'm still spending hours and days trying to do it,no way....no activity on TDI or TDO) here ,once ,more the things that i did: i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not easy to test it (soldering wires on a bga as i do is even worse ...)but it looks that it should be enough for the core,correct???or i need to i connected in 7 points the 3.3VCCO(A2,B2,B12 , A13,G12,N1,M2) and the ground in 3 points(A1,J1,N12) i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level amplifier) I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same result..... I left M0 and M2 open,and them are high,M1 tied to ground,this for choosing boundary scan mode using the debug chain utility i verified that the signals are working but i noticed that there is no movement on TMS,and of course on TDO there is something else missing? Thank you to everyone in the group that will help me or just will read this Diego
Reply by ●July 3, 20062006-07-03
>Aurelian Lazarut schrieb: > > did you connect Vccaux? (2.5V) > Aurash > blisca wrote: > > >for reading the device ID how should the PROGRAM pin be ? > -- > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324Dear Xilinx System Verification Engineer! It stands "XCV200" in the subject from the OP, and that means: "Virtex Family" ! .. and Virtex Family has no VCCAUX !!! I belive that for Xilinx people the "Virtex" is really considered dead - how could be otherwise explainable that Xilinx has obsoleted SystemACE SC what means that an MCS (softcore) is obsoleted!! the only reason could be that Virtex silicon is no longer manufactured what also explains the availability an silly pricing of it. It was really surprising for me to see that ISE 8.1 has silently dropped systemACE SC support! Antti http://antti-brain.com
Reply by ●July 3, 20062006-07-03
Hi Annti, I was mis leaded because of this statement from the original post: "i connected just one 1.8V supply to the VCCINT of the fpga" hence my assumption that a virtexE was in question. Aurash Antti wrote:>>Aurelian Lazarut schrieb: >> >>did you connect Vccaux? (2.5V) >>Aurash >>blisca wrote: >> >> >> >>>for reading the device ID how should the PROGRAM pin be ? >>> >>> >>-- >> __ >>/ /\/\ Aurelian Lazarut >>\ \ / System Verification Engineer >>/ / \ Xilinx Ireland >>\_\/\/ >> >>phone: 353 01 4032639 >>fax: 353 01 4640324 >> >> > >Dear Xilinx System Verification Engineer! > >It stands "XCV200" in the subject from the OP, and that means: >"Virtex Family" ! .. and Virtex Family has no VCCAUX !!! > >I belive that for Xilinx people the "Virtex" is really considered dead >- >how could be otherwise explainable that Xilinx has obsoleted SystemACE >SC >what means that an MCS (softcore) is obsoleted!! the only reason could >be >that Virtex silicon is no longer manufactured what also explains the >availability >an silly pricing of it. > >It was really surprising for me to see that ISE 8.1 has silently >dropped >systemACE SC support! > >Antti >http://antti-brain.com > > >-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
Reply by ●July 3, 20062006-07-03
blisca schrieb:> Thank you again to all that answered or only spent their time reading this > post. > Antti wrote > > prog_b needs to have an pullup to logic high level > > about pull-ups: > wich high level?1.8V or 3.3V? > (i forgot to say in the subject that i'm working,but i should better say > "crying",on a xcv200E )uups! I yielled at Xilinx guy about him commenting about VCCAUX, well on Virtex-E it is also not available so it is no problem anyway. again - M0,M1,M2 - DONT CARE pullup of PROG_B - either 1.8 or 3.3V should be ok but even with PROG_B pulled down JTAG chain should be scannable can you see the IDCODE when you scan the chain? Antti
Reply by ●July 3, 20062006-07-03
Thank you again to all that answered or only spent their time reading this post. Antti wrote> prog_b needs to have an pullup to logic high levelabout pull-ups: wich high level?1.8V or 3.3V? (i forgot to say in the subject that i'm working,but i should better say "crying",on a xcv200E ) and what about the MODE?should i use pull-ups or not? this table is still not clear to me......does it means that if i dont use external pull-ups resistors(wich value?) should i use 1 0 1 with M1 connected to ground and M2 and M0 connected directly to.......VINT or VCCO?In few words,what is the correct mode for phisically implement the correct configuration? Configuration Mode M2 M1 M0 Pull-ups Master Serial 0 0 0 No Slave Serial 1 1 1 No SelectMAP 1 1 0 No Boundary Scan 1 0 1 No <---------- Master Serial (w/pull-ups) 1 0 0 Yes Slave Serial (w/pull-ups) 0 1 1 Yes SelectMAP (w/pull-ups) 0 1 0 Yes Boundary Scan (w/pull-ups) 0 0 1 Yes <----------> > xilinx datasheet says it has internal pullup but on Virtex family JTAG > config > does not work without external pullup, that is the JTAG chain is > accessible > but configuratio fails. > > minimal connections are > > GND <--------done > VCCINT <--------done,itlooks ohmically connected to every VCCINT pin> VCCIO in the bank that supply JTAG <--------done,connecteds to the 3VCCIO of Banks 2 & 3 B12, G11, M13> PROG_B pullup <--------not done,doingit soon> JTAG pins <--------done andverified> > thats all! > > if those connections are ok the FPGA should get configured over JTAG > > Antti > http://antti-brain.com >
Reply by ●July 3, 20062006-07-03
Aurelian Lazarut schrieb:> Hi Annti, > I was mis leaded because of this statement from the original post: > "i connected just one 1.8V supply to the VCCINT of the fpga" > hence my assumption that a virtexE was in question. > AurashWell to MY knowledge Virtex-E has also no VCCAUX !? Antti PS To OP, I probably did not say strong enough: for reading of IDCODE over JTAG the prog_b is "DONT CARE" only issue is (or can be) that actualy configuration may fail without pullup.
Reply by ●July 3, 20062006-07-03
"blisca" <blisca@tiscali.it> wrote in message news:44a93c14$0$3119$4fafbaef@reader1.news.tin.it...> for reading the device ID how should the PROGRAM pin be ? > > thank you all > (i'm still spending hours and days trying to do it,no way....no activity > on > TDI or TDO) > >[snip] TDI is the input and TDO is the output (at the FPGA). If you don't see activity (ever) on the FPGA's TDI pin then this is your problem. You may have the JTAG controller's TDI/TDO pins swapped. Are you using "flying leads" to connect the controller to your FPGA board? It's easy to get those wrong. I suggest you disconnect the controller from your board, and see which of the controller leads (TDI or TDO) wiggles when it attempts to communicate. The one that wiggles should be connected to the FPGA's TDI pin. Bob
