Inferring multiple-DSP48 pipelined multiplier in VHDL

Hi Guys,

I'm having trouble with the following problem:

I'm trying to create a 35x35 signed multiplier from DSP48s, inferring
pipelining in VHDL by adding registers after the multilplication
operation as seen below in the VHDL I'm using.

The problem is that when I synthesise, though I can see that the
synthesiser has noticed that it can shift registers about:

Synthesizing (advanced) Unit <signed_mult_TOP>.
	Found pipelined multiplier on signal <mult_inst/_n0000>:
		- 2 pipeline level(s) found in a register connected to the multiplier
macro output.
		Pushing register(s) into the multiplier macro.

		- 2 pipeline level(s) found in a register on signal <mult_inst/A2>.
		Pushing register(s) into the multiplier macro.

		- 2 pipeline level(s) found in a register on signal <mult_inst/B2>.
		Pushing register(s) into the multiplier macro.

the clock rate achieved is still only a meagre 81.171MHz. I'll save my
half-baked hypotheses for now and see if anyone knows what's up here.
Any help you can give would be very much appreciated.

Robin

VHDL:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY signed_mult_35x35 IS
	generic (PIPE: natural);
	port (
	clk: IN std_logic;
	a: IN signed(34 downto 0);
	b: IN signed(34 downto 0);
	o: OUT signed(69 downto 0));
END signed_mult_35x35;

ARCHITECTURE signed_mult_35x35_a OF signed_mult_35x35 IS

signal A2 :	signed(34 downto 0);

signal B2 :	signed(34 downto 0);

subtype mult_result is signed(69 downto 0);
type mult_result_array is array (0 to PIPE - 2) of mult_result;



signal pipeline_array : mult_result_array;

BEGIN

o <= pipeline_array(PIPE - 2);

reg: process(CLK) begin
	if(rising_edge(CLK)) then
    A2 <= a;
	B2 <= b;
	pipeline_array(0) <= A2 * B2;
	for i in 1 to PIPE - 2 loop
	  pipeline_array(i)	<= pipeline_array(i-1);
	end loop;
		-- Registering should be fused into DSP48-inferred multiply operation
  end if;
end process;

END signed_mult_35x35_a;