High-speed DAC/ADC with FPGA

Hi folks

I'm working with an Altera Stratix ep1s10 on a development board. The
data sheet says the IO can operate at rates up to 800 MSPS. If I have a
look on the internet, I see DAC and ADC technology going up to 400
MSPS.

My application is software defined radio, where the general mantra is
to do as little analog front-end as possible, i.e. sample as fast as
you can.

What are the limits on my conversion rates? I doubt it's even remotely
possible for me to do data conversion at 400 MSPS? My main concern is
the PCB layout, with about 15cm of track and a header between the FPGA
and the conversion chips. Crosstalk, EMI and impedance matching are all
things I know very little about.

Is there a more appropraiate group to post on?

Thanks in advance,
Richard

rnbrady wrote:
> Hi folks
>
> I'm working with an Altera Stratix ep1s10 on a development board. The
> data sheet says the IO can operate at rates up to 800 MSPS. If I have a
> look on the internet, I see DAC and ADC technology going up to 400
> MSPS.
>
> My application is software defined radio, where the general mantra is
> to do as little analog front-end as possible, i.e. sample as fast as
> you can.
>
> What are the limits on my conversion rates? I doubt it's even remotely
> possible for me to do data conversion at 400 MSPS? My main concern is
> the PCB layout, with about 15cm of track and a header between the FPGA
> and the conversion chips. Crosstalk, EMI and impedance matching are all
> things I know very little about.
>
> Is there a more appropraiate group to post on?
>
> Thanks in advance,
> Richard

Crossposted to s.e.d.
There's no reason you can't sample at 400MS/s with the right parts and
proper layout. At those speeds you do have to be very careful about
layout, and differential sampling is probably a *very* good idea.

More details are really needed:


What type of header are you talking about? I have run signals at 5Gb/s
through connectors designed for the task with little loss and very low
crosstalk, but they aren't cheap. Is this an existing header?

Does this mean you want to run wires, or are you making a circuit board
for the A-D? You are unlikely to get high data rates with handwired
circuitry (you can get reasonably high speeds, but not too high unless
you are an expert in wirewrap and routing ;).

You say you are using a development board. What documentation is there
for it? Point us at some details if you have them.

What is the interface from your A-D converter(s)? Serial? Parallel?
Parallel may take more lines, but it also gives the lowest data rate.
There are also tricks of synchronised sampling (using multiple
converters, suitably calibrated) to increase the effective sample rate,
should that be necessary. On that subject, is there a particular A-D
device you have in mind, or are you open to suggestions?

What signal frequency range are you particularly interested in getting?
If you are not sure of what to use, this will let others help you
choose an appropriate device.

Even if you sample with a decent A-D, you should still (in my opinion)
put an anti-aliasing filter on the front end, and buffering to prevent
loading. (Some parts have them internally). Unless you have a buffered
output from something, you are probably going to have to put down at
least some analog circuitry apart from the A-D(s).

Speaking of that, what RF device did you intend to use to get the
signal in the first place?

Answer those (reply to both groups) and some of the denizens of s.e.d.
will no doubt dispense some ideas, and no doubt ask more questions.

Cheers

PeteS

Many A/D converters have a double-width digital interface, which
reduces the FPGA capture rate by a factor two (but doubles the number
of bits)
I have seen sample rates of 1 Gsps interfaced to FPGAs (guess which
ones).
Make sure that the sampling clock is as clean as possible. Any jitter
will severely impact your analog noise floor, i.e. will reduce the
dynamic range.

Peter Alfke, Xilinx
====================
rnbrady wrote:
> Hi folks
>
> I'm working with an Altera Stratix ep1s10 on a development board. The
> data sheet says the IO can operate at rates up to 800 MSPS. If I have a
> look on the internet, I see DAC and ADC technology going up to 400
> MSPS.
>
> My application is software defined radio, where the general mantra is
> to do as little analog front-end as possible, i.e. sample as fast as
> you can.
>
> What are the limits on my conversion rates? I doubt it's even remotely
> possible for me to do data conversion at 400 MSPS? My main concern is
> the PCB layout, with about 15cm of track and a header between the FPGA
> and the conversion chips. Crosstalk, EMI and impedance matching are all
> things I know very little about.
>
> Is there a more appropraiate group to post on?
> 
> Thanks in advance,
> Richard

PeterSmith1954@googlemail.com wrote:
> rnbrady wrote:
> > Hi folks
> >
> > I'm working with an Altera Stratix ep1s10 on a development board. The
> > data sheet says the IO can operate at rates up to 800 MSPS. If I have a
> > look on the internet, I see DAC and ADC technology going up to 400
> > MSPS.
> >
> > My application is software defined radio, where the general mantra is
> > to do as little analog front-end as possible, i.e. sample as fast as
> > you can.
> >
> > What are the limits on my conversion rates? I doubt it's even remotely
> > possible for me to do data conversion at 400 MSPS? My main concern is
> > the PCB layout, with about 15cm of track and a header between the FPGA
> > and the conversion chips. Crosstalk, EMI and impedance matching are all
> > things I know very little about.
> >
> > Is there a more appropraiate group to post on?
> >
> > Thanks in advance,
> > Richard
>
> Crossposted to s.e.d.
> There's no reason you can't sample at 400MS/s with the right parts and
> proper layout. At those speeds you do have to be very careful about
> layout, and differential sampling is probably a *very* good idea.

Software radio makes life a lot more interesting than regular A/D
conversion.

The sorts of circuits that run at 400MSPS tend to be quite potent radio
transmitters, unless you are very careful about circuit layout -
classical radios had to bury the local oscillator in a shielded metal
box to stop it radiating into your antenna.

Presumably this is a soluble problem, but the OP doesn't seem to know
it exists, which could complicate life.

-- 
Bill Sloman, Nijmegen

Hi guys

Thanks for the helpful replies.


> More details are really needed:
>
> What type of header are you talking about? I have run signals at 5Gb/s
> through connectors designed for the task with little loss and very low
> crosstalk, but they aren't cheap. Is this an existing header?

The headers are existing. They are standard beak-away headers.

> Does this mean you want to run wires, or are you making a circuit board
> for the A-D? You are unlikely to get high data rates with handwired
> circuitry (you can get reasonably high speeds, but not too high unless
> you are an expert in wirewrap and routing ;).

I plan to have a PCB made. We have facilities for two layer PCB
manufacturing.

> You say you are using a development board. What documentation is there
> for it? Point us at some details if you have them.

I'm working with an Altera dev kit:
http://www.altera.com/products/devkits/altera/kit-nios_1S10.html

There is tons of documentaion for the NiosII embedded CPU on this dev
kit but almost no documnetation on the board itself.

> What is the interface from your A-D converter(s)? Serial? Parallel?

I'd find it simpler to do parallel, there's no shortage of pins.

> Parallel may take more lines, but it also gives the lowest data rate.
> There are also tricks of synchronised sampling (using multiple
> converters, suitably calibrated) to increase the effective sample rate,
> should that be necessary. On that subject, is there a particular A-D
> device you have in mind, or are you open to suggestions?

Completely open.

> What signal frequency range are you particularly interested in getting?
> If you are not sure of what to use, this will let others help you
> choose an appropriate device.

I'd like to capture and generate signals anywhere from 10kHz to 100MHz.
It would be great if I could reach 450MHz with some mixing at the front
end. I don't really need more than 1MHz at a time. So a lower rate with
a NCO + mixer might be a better bet. The basic idea to to be able to
receice and transmit commercial FM and AM, plus some walkie-talkie FM,
and maybe some HAM radio, all with as little HW as possible.

>
> Even if you sample with a decent A-D, you should still (in my opinion)
> put an anti-aliasing filter on the front end, and buffering to prevent
> loading. (Some parts have them internally). Unless you have a buffered
> output from something, you are probably going to have to put down at
> least some analog circuitry apart from the A-D(s).

This is fine, I simply want to keep it to a minimum.

> Speaking of that, what RF device did you intend to use to get the
> signal in the first place?

An antenna.

>
> Answer those (reply to both groups) and some of the denizens of s.e.d.
> will no doubt dispense some ideas, and no doubt ask more questions.

Thanks again. I really appreciate your input.

Richard

rnbrady wrote:
> Hi guys
> 
> Thanks for the helpful replies.
> 
> 
>> More details are really needed:
>>
>> What type of header are you talking about? I have run signals at 5Gb/s
>> through connectors designed for the task with little loss and very low
>> crosstalk, but they aren't cheap. Is this an existing header?
> 
> The headers are existing. They are standard beak-away headers.
> 
>> Does this mean you want to run wires, or are you making a circuit board
>> for the A-D? You are unlikely to get high data rates with handwired
>> circuitry (you can get reasonably high speeds, but not too high unless
>> you are an expert in wirewrap and routing ;).
> 
> I plan to have a PCB made. We have facilities for two layer PCB
> manufacturing.
> 

I would expect you to need more than two layers for a high speed ADC card.

>> You say you are using a development board. What documentation is there
>> for it? Point us at some details if you have them.
> 
> I'm working with an Altera dev kit:
> http://www.altera.com/products/devkits/altera/kit-nios_1S10.html
> 
> There is tons of documentaion for the NiosII embedded CPU on this dev
> kit but almost no documnetation on the board itself.

The schematics for the card are available.  If it is like the Cyclone 
Nios II card, then there are buffers on the pins connected to the 
headers, which will severely limit the speed of these pins.

> 
>> What is the interface from your A-D converter(s)? Serial? Parallel?
> 
> I'd find it simpler to do parallel, there's no shortage of pins.
> 
>> Parallel may take more lines, but it also gives the lowest data rate.
>> There are also tricks of synchronised sampling (using multiple
>> converters, suitably calibrated) to increase the effective sample rate,
>> should that be necessary. On that subject, is there a particular A-D
>> device you have in mind, or are you open to suggestions?
> 
> Completely open.
> 
>> What signal frequency range are you particularly interested in getting?
>> If you are not sure of what to use, this will let others help you
>> choose an appropriate device.
> 
> I'd like to capture and generate signals anywhere from 10kHz to 100MHz.
> It would be great if I could reach 450MHz with some mixing at the front
> end. I don't really need more than 1MHz at a time. So a lower rate with
> a NCO + mixer might be a better bet. The basic idea to to be able to
> receice and transmit commercial FM and AM, plus some walkie-talkie FM,
> and maybe some HAM radio, all with as little HW as possible.
> 
>> Even if you sample with a decent A-D, you should still (in my opinion)
>> put an anti-aliasing filter on the front end, and buffering to prevent
>> loading. (Some parts have them internally). Unless you have a buffered
>> output from something, you are probably going to have to put down at
>> least some analog circuitry apart from the A-D(s).
> 
> This is fine, I simply want to keep it to a minimum.
> 
>> Speaking of that, what RF device did you intend to use to get the
>> signal in the first place?
> 
> An antenna.
> 
>> Answer those (reply to both groups) and some of the denizens of s.e.d.
>> will no doubt dispense some ideas, and no doubt ask more questions.
> 
> Thanks again. I really appreciate your input.
> 
> Richard
> 

On a sunny day (10 Jul 2006 15:42:18 -0700) it happened bill.sloman@ieee.org
wrote in <1152571338.767516.262410@75g2000cwc.googlegroups.com>:
classical radios had to bury the local oscillator in a shielded metal
>box to stop it radiating into your antenna.

Dunno what you call 'classical', but even my tube communications receiver
in the sixties had no 'separate box' for the LO.

A RF pre-amp, folowed by a mixer would give plenty isolation.
The good old 'ECH81 ?? osc mixer tubes had it all in obne tube and no
RF pre.
Those were commercial radios.
No normal transistor radio has a boxed LO.

Modern TV tuners using dual gate MOSFETS have it all on one PCB....
Very old UHF / VHF tuners had a separate section for the LO.
But the reason was likely one of tuning, after all there was 38 MHz or
so offset.

It is true that with many transistor radios you can jam a AM MW station by
tuning 455 kHz (or whatever) next to it, but it only works on a few
meters distance.
 

Jan Panteltje wrote:
> On a sunny day (10 Jul 2006 15:42:18 -0700) it happened bill.sloman@ieee.org
> wrote in <1152571338.767516.262410@75g2000cwc.googlegroups.com>:

> > classical radios had to bury the local oscillator in a shielded metal
> >box to stop it radiating into your antenna.
>
> Dunno what you call 'classical', but even my tube communications receiver
> in the sixties had no 'separate box' for the LO.
>
> A RF pre-amp, folowed by a mixer would give plenty isolation.
> The good old 'ECH81 ?? osc mixer tubes had it all in one tube and no
> RF pre.

I'll bet that there was some internal shielding within the ECH81
oscillator/mixer tube.

> Those were commercial radios.
> No normal transistor radio has a boxed LO.

I'll take your word for it - I haven't opened up a transistor radio for
some years now.
Careful printed circuit layout, and tricks like generating
complementary/balanced signal pairs and routing them close together can
obviously minimise the radiation from the local oscillator to the point
where the shielded metal box is no longer necessary.

The point is that you have to know you need to be this careful,and you
ought to read up on the tricks of the trade. Reinventing the wheel
takes time and gives loads of opportunities to invent a whole clas of
constant cross-section rollers that don't work as well.

The OP would find it easier to get a good layout on a four or six layer
board with a buried ground plane or two, but a double-sided board
should be practical, with careful layout.

> Modern TV tuners using dual gate MOSFETS have it all on one PCB....
> Very old UHF / VHF tuners had a separate section for the LO.
> But the reason was likely one of tuning, after all there was 38 MHz or
> so offset.
>
> It is true that with many transistor radios you can jam a AM MW station by
> tuning 455 kHz (or whatever) next to it, but it only works on a few
> meters distance.

It is rather difficult to keep the electronics of a radion more than a
few metres away from  its antenna.

-- 
Bill Sloman, Nijmegen

On a sunny day (11 Jul 2006 03:33:50 -0700) it happened bill.sloman@ieee.org
wrote in <1152614030.638069.323220@b28g2000cwb.googlegroups.com>:
>> It is true that with many transistor radios you can jam a AM MW station by
>> tuning 455 kHz (or whatever) next to it, but it only works on a few
>> meters distance.
>
>It is rather difficult to keep the electronics of a radion more than a
>few metres away from  its antenna.

Well, point is, it will not jam 'itself' (for all I know).
You can jam an OTHER radio, try it, it is easy, works on FM too.
Way of topic anyways, I have looked in Tek scopes with fast AD,
not very special layout I could see, just keep it logical...
1G samples/second is normal these days.
As soon as it is 'digital' many problems become simpler.

But anyways, maybe I am a bit old-fashinoned (say older), IMO
some RF pre (selectivity and gain) before any digitising in radio makes
some sense, especially for weak signals.
I do notice a trend to connect the antenna directly to the AD chip ;-)

LC is nice.

National Semiconductor has a development board for their dual
ADC08D1500 dual 1500 MSPS, 8 bit ADCs that includes a Xilinx V4 FPGA
and a USB interface controller on board. The dual converters can be
automatically interleaved on the same input for 3000 MSPS. 1:2
demultiplexed LVDS outputs to the FPGA. I've heard they and Altera are
also working on a similar development board.

Andy

Peter Alfke wrote:
> Many A/D converters have a double-width digital interface, which
> reduces the FPGA capture rate by a factor two (but doubles the number
> of bits)
> I have seen sample rates of 1 Gsps interfaced to FPGAs (guess which
> ones).
> Make sure that the sampling clock is as clean as possible. Any jitter
> will severely impact your analog noise floor, i.e. will reduce the
> dynamic range.
>
> Peter Alfke, Xilinx
> ====================
> rnbrady wrote:
> > Hi folks
> >
> > I'm working with an Altera Stratix ep1s10 on a development board. The
> > data sheet says the IO can operate at rates up to 800 MSPS. If I have a
> > look on the internet, I see DAC and ADC technology going up to 400
> > MSPS.
> >
> > My application is software defined radio, where the general mantra is
> > to do as little analog front-end as possible, i.e. sample as fast as
> > you can.
> >
> > What are the limits on my conversion rates? I doubt it's even remotely
> > possible for me to do data conversion at 400 MSPS? My main concern is
> > the PCB layout, with about 15cm of track and a header between the FPGA
> > and the conversion chips. Crosstalk, EMI and impedance matching are all
> > things I know very little about.
> >
> > Is there a more appropraiate group to post on?
> > 
> > Thanks in advance,
> > Richard