Routing Information of Xilinx's Virtex-II FPGA

Hi All,

 I am seeking for following information regarding Virtex-II FPGA:

 1. Is it possible to know exact delay information of each type of
segment (signle line, double, hex lines etc.) present in Virtex-II?

 2. Is it possible to now exact delay information of Programmable
Interconnect Point(PIP) present between any two segments in Virtex-II?

 I tried to get above information from Data Sheet provided by Xilinx
but did not get it. I will be very thankfull if somebody can give me
pointers to get the above information.

Regards,
Manoj