Virtex 4, LVDS I/O: Sanity check please

PeteS,

There is one thing you are missing:  the package.  You have no control 
over that.

The value is less important.  "A good match" is between 2:1.  Really. 
Just run the simulations and you can see that happenening.

Your tricks with the pcb are all lost because the package has a 1" long 
50 ohm trace in it, with a capacitive load at its end (the transistors 
in their off state - not driving).

If only the pad to the die where directly mounted to the pcb.  But that 
is not possible with the die we have today (with as many as 1700 pcb 
bumps, and perhaps more than 10,000 package bumps).

Austin

PeteS wrote:

> Austin Lesea wrote:
> 
>>All,
>>
>>Any external resistor, no how well implemented is ever as good as an
>>internal termination.  It has to do with the short stub to the resistor
>>which is unavoidable being a source of reflections.
> 
> 
> True in a literal sense, provided one can get the precision, which is
> not that easy in a standard IC.
> That said, the parasitics you refer to are not an issue for an 0402
> device at 5Gb/s signalling (far higher speeds than the OP desires to
> deal with in this case) - any such parasitics are swamped by other
> issues of moving a signal across ciruit board (depends on the specific
> circuit board, of course, but in this case I expect the project to be
> FR-4 based).
> 
> There are methods of dealing with the 'stub' (by necking the track to
> the pad and trickery with adjacent grounds on the same layer) which
> reduce it to the realm of effectively non-existent.
> 
> For this particular case, if you look at the part I suggested, the only
> discontinuity would be at the ball itself, and that is a minor issue.
> 
> Cheers
> 
> PeteS
> 
> 
> 
>>That aside, the DCI for SSTL/HSTL is a resistance to ground from the
>>rails, so it uses power (more than 200 IO's and we are talking some
>>serious number of watts).
>>
>>Have you considered using LVCMOS DCI in a bidirectional mode?
>>
>>If you would like to see a signal integrity program result, email me
>>directly (or request one from the hotline).
>>
>>Talking about it won't solve your problem.  You have to do some real SI
>>engineering for any custom IO requirement.  In my opintion, it should be
>>done for any IO requirement.
>>
>>Austin
>>
>>Austin
>>
>>PeteS wrote:
>>
>>
>>>John Adair wrote:
>>>
>>>
>>>>Your biggest issue is not the top surface area for the resistor site
>>>>but the via space and extra routing needed to connect resistors. The
>>>>vias especially will have significant routing effects. Even using a
>>>>microvia blocks the path for potentially an extra signal. Conventional
>>>>vias block 2 traces worth in our standard technology. BGA resistor
>>>>packs whilst small tend not to have a good run of routing them and
>>>>generally increase layer count to achieve the end result.
>>>>
>>>>John Adair
>>>>Enterpoint Ltd.
>>>
>>>
>>>Depends on what is being routed, of course.
>>>
>>>In this particular application, the signal can go in and out very
>>>easily (1 track between balls for each ball position) and no vias at
>>>all are required.
>>>
>>>In a parallel termination case, things are different, but for a series
>>>terminator, the devices I have used work just fine with no extra layer
>>>count required. Indeed, the part manufacturers are aware of the issue
>>>that saving space for the package but providing poor access negates any
>>>advantage of the package size, so parts are appearing that have decent
>>>routing ability.
>>>
>>>Cheers
>>>
>>>PeteS
>>>
>>>
>>>
>>>
>>>>PeteS wrote:
>>>>
>>>>
>>>>>John Adair wrote:
>>>>>
>>>>>
>>>>>>Standards like SSTL are good for this due to the low signal swing. The
>>>>>>biggest decision is if to use DCI which burns more power in the V4 or to use
>>>>>>external resistors which take board area and make routing more difficult.
>>>>>>
>>>>>>The other decision is weither you use source synchronous clocking or a
>>>>>>common clock approach. At 150 Mhz the common clock is slightly marginal
>>>>>>depending on how long tracks are, speed grade, etc. unless you use some DCM
>>>>>>based techniques. You can generate a clock that is offset from the common
>>>>>>clock a little by using a DCM and use that as clock for register input to
>>>>>>gain more time. Alternatively you can use a DCM to null out the clock to
>>>>>>output time and get more margin from that.
>>>>>>
>>>>>>John Adair
>>>>>>Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development
>>>>>>Board.
>>>>>>http://www.enterpoint.co.uk
>>>>>>
>>>>>>
>>>>>>"Marc Reinig" <Marco@newsgroups.nospam> wrote in message
>>>>>>news:44bc1fed@darkstar...
>>>>>>
>>>>>>
>>>>>>>I have a project where I will have a large array of V4 FPGAs.  Each chip is
>>>>>>>intended to connect to its four orthogonal neighbors with no intervening
>>>>>>>logic.  I would like the number of bus connections between chips in any
>>>>>>>direction in the array to be 150 (600 total I/O per chip).  The connections
>>>>>>>will be bi-directional.  The distance between chips will be the minimum I
>>>>>>>can have with sockets, heat sinks (with individual fans), good layout and
>>>>>>>noise control.  Some of the lines, what ever is necessary, will be used for
>>>>>>>clock and framing for the bus data signals.  I would like to use DDR.
>>>>>>>During bus transfers, all the lines on opposite sides of the chip will be
>>>>>>>operating and the other two sides will be quiescent.  I'm hoping for a bus
>>>>>>>clock of 150 MHz.
>>>>>>>
>>>>>>>
>>>>>>>Comments? ;=)
>>>>>>>
>>>>>>>Marco
>>>>>>>________________________
>>>>>>>Marc Reinig
>>>>>>>UCO/Lick Observatory
>>>>>>>Laboratory for Adaptive Optics
>>>>>>>
>>>>>>>
>>>>>
>>>>>If Marc uses SSTL, and uses resistive terminators, I would agree it
>>>>>takes board space, but I disagree it would make routing significantly
>>>>>more difficult, except for the sheer number of devices. In a point to
>>>>>point situation only a series terminator is really required for speeds
>>>>>up to at least 200MHz / 400Mb/s (I've done it).
>>>>>
>>>>>Assuming these busses would be bidirectional, external series resistors
>>>>>would [arguably, at least] actually be better in reducing EMI and
>>>>>reflections than just DCI (less power too) assuming the devices are
>>>>>close together (of the order of perhaps 4 inches or less). Much really
>>>>>depends on the distance. I've used BGA style resistor packs that cram
>>>>>more resistors into the device than can be done in multipack type SMT
>>>>>devices. Apart from that, the tiny quad pack devices are particularly
>>>>>sensitive to even slightly imperfect chip shooters and have a nasty
>>>>>tendency to crack the resistor, particularly at the ends of the device.
>>>>>
>>>>>CTS corp makes a particularly nice range of devices
>>>>>(http://www.ctscorp.com/components/clearone.asp) [I have no affiliation
>>>>>with them except for having used the parts in the past].
>>>>>
>>>>>Cheers
>>>>>
>>>>>PeteS
>>>
>>>
>