Which PCI core for Cyclone II board?

Does anyone have experience with more than one of the PCI cores out
there?  I'm working a PCI card that's still in the early stages of the
design.  I'm hoping to be able to do pretty much everything on a single
Altera FPGA - most likely a Cyclone II device.

I've looked at the PCI Compiler from Altera.  It seems very poorly
documented, which I think will make the backend difficult to develop
and complicated.  The one from opencores.org looks like it's easier to
use, better documented, and has the advantage of being LGPL.  I haven't
looked at the one from Eureka much.

Any comment's regarding PCI compliance, ease of use, compatability with
Altera parts, etc?

"Brian McFarland" <brian.mcf1985@gmail.com> schrieb im Newsbeitrag 
news:1153248948.387051.197670@p79g2000cwp.googlegroups.com...
> Does anyone have experience with more than one of the PCI cores out
> there?  I'm working a PCI card that's still in the early stages of the
> design.  I'm hoping to be able to do pretty much everything on a single
> Altera FPGA - most likely a Cyclone II device.
>
> I've looked at the PCI Compiler from Altera.  It seems very poorly
> documented, which I think will make the backend difficult to develop
> and complicated.  The one from opencores.org looks like it's easier to
> use, better documented, and has the advantage of being LGPL.  I haven't
> looked at the one from Eureka much.
>
> Any comment's regarding PCI compliance, ease of use, compatability with
> Altera parts, etc?
>

the easiest is the free PCI target from lattice, free download

I have used it on more than 5 different boards, altera and xilinx based
it has worked almost always first time tried - just set pin constraints and 
thats it

there are other free alternatives as well, but the lattice pci target is the 
simplest

Antti 

Brian McFarland wrote:

> Any comment's regarding PCI compliance, ease of use, compatability with
> Altera parts, etc?

I've used the opencores PCI core on an Altera Cyclone II (EP2C35) dev board.

No implementation/compatibility issues at all really. Nice if you have 
wishbone peripherals you want to hook up on the back end - very easy to 
get going. Had opencores DMA mastering over PCI too.

Performance is another issue. If you're looking to push PCI burst 
transfers to the limit, then it's not so straightforward. Not saying it 
can't be done, but it will take some effort.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Brian McFarland schreef:

> I've looked at the PCI Compiler from Altera.  It seems very poorly
> documented, which I think will make the backend difficult to develop
> and complicated.

The Altera PCI Compiler has an option to generate it as a Avalon
peripheral, which then enables SOPC Builder to do the back-end work for
you. This is as easy as it gets.

SOPC Builder Ready:
http://www.altera.com/products/ip/certifications/sopc/ip-sopc.html

SOPC Builder:
http://www.altera.com/products/software/products/sopc/sop-index.html

Look in the PCI Compiler installation folder for the 'sopc_flow' and
you will find an ready to use example.

Kind regards, Karl.

sorry antti,
but do you mean that at lattice they have a downloadable pci ip 
retargettable to any fpga? (i.e  rtl code?) if yes could put here the link?



Antti Lukats ha scritto:
> "Brian McFarland" <brian.mcf1985@gmail.com> schrieb im Newsbeitrag 
> news:1153248948.387051.197670@p79g2000cwp.googlegroups.com...
>> Does anyone have experience with more than one of the PCI cores out
>> there?  I'm working a PCI card that's still in the early stages of the
>> design.  I'm hoping to be able to do pretty much everything on a single
>> Altera FPGA - most likely a Cyclone II device.
>>
>> I've looked at the PCI Compiler from Altera.  It seems very poorly
>> documented, which I think will make the backend difficult to develop
>> and complicated.  The one from opencores.org looks like it's easier to
>> use, better documented, and has the advantage of being LGPL.  I haven't
>> looked at the one from Eureka much.
>>
>> Any comment's regarding PCI compliance, ease of use, compatability with
>> Altera parts, etc?
>>
> 
> the easiest is the free PCI target from lattice, free download
> 
> I have used it on more than 5 different boards, altera and xilinx based
> it has worked almost always first time tried - just set pin constraints and 
> thats it
> 
> there are other free alternatives as well, but the lattice pci target is the 
> simplest
> 
> Antti 
> 
> 

antonio bergnoli schrieb:

> sorry antti,
> but do you mean that at lattice they have a downloadable pci ip
> retargettable to any fpga? (i.e  rtl code?) if yes could put here the link?
>
>
>
> Antti Lukats ha scritto:

sure get it here

http://www.latticesemi.com/products/intellectualproperty/referencedesigns/pcitarget32bit33mhz.cfm

100% verilog source included!

Antti
http://antti-brain.com

Thanks!!
and could you suggest a good staring poit to learn pci standard? better 
if for free..:-)

Antti ha scritto:
> antonio bergnoli schrieb:
> 
>> sorry antti,
>> but do you mean that at lattice they have a downloadable pci ip
>> retargettable to any fpga? (i.e  rtl code?) if yes could put here the link?
>>
>>
>>
>> Antti Lukats ha scritto:
> 
> sure get it here
> 
> http://www.latticesemi.com/products/intellectualproperty/referencedesigns/pcitarget32bit33mhz.cfm
> 
> 100% verilog source included!
> 
> Antti
> http://antti-brain.com
> 

Mark McDougall wrote:
> No implementation/compatibility issues at all really. Nice if you have
> wishbone peripherals you want to hook up on the back end - very easy to
> get going. Had opencores DMA mastering over PCI too.
>
> Performance is another issue. If you're looking to push PCI burst
> transfers to the limit, then it's not so straightforward. Not saying it
> can't be done, but it will take some effort.

That's another thing i meant to ask about in my original post.  Is
there noticible performance difference between the different available
cores?

This is my experience with anything PCI related, so I'm still not very
clear on whether I can get away with a target, or if I'll need to
mastering/DMA capabilities.  I know that theoretically, the max tranfer
rate of the bus is 133 MB/s w/ 33MHz systems.  The intended customer of
this thing is going for low cost, so I'm not going to assume that it
will be used with a computer that supports 66Mhz or 64-bit transfers.
Ideally, I would like to be able to guarantee 54 MB/s with pretty much
equal I/O rates (27MB/s into and out of the device). Most of the time,
rates should be lower than that, but just about the max I could ever
need it to be.  This card will probably be the only thing on the PCI
bus of the PC it's plugged into, and the primary purpose of the PC will
be to process the data to & from this device, so having moderately high
CPU usage requirements is not much of a concern.

Hi Brian,

An important consideration regarding the PCI bus (say, in a desktop PC) is
that you generally cannot make any guarantees about bandwidth.  There are
too many things outside of your control -- the O/S, other devices using the
bus, the performance capabilities of the host bridge device...

That "133 MBytes/sec for PCI32/33" is the physical bus bandwidth -- how much
data could possibly fly over the bus.  It is not an indicator of what your
device may realize in a typical system.

If you need performance, and your host is going to be x86 based with a
commodity chipset (certainly not "perfect"), you absolutely must include
some kind of bus mastering capability.  For all practical purposes, it will
be very difficult to get any kind of data burst initiated by the CPU to your
device target.  For that reason, a target will not suffice unless you are
building something that only needs a dribble of data -- a standard serial
port, or an LED flasher.  :)

Eric

> This is my experience with anything PCI related, so I'm still not very
> clear on whether I can get away with a target, or if I'll need to
> mastering/DMA capabilities.  I know that theoretically, the max tranfer
> rate of the bus is 133 MB/s w/ 33MHz systems.  The intended customer of
> this thing is going for low cost, so I'm not going to assume that it
> will be used with a computer that supports 66Mhz or 64-bit transfers.
> Ideally, I would like to be able to guarantee 54 MB/s with pretty much
> equal I/O rates (27MB/s into and out of the device). Most of the time,
> rates should be lower than that, but just about the max I could ever
> need it to be.  This card will probably be the only thing on the PCI
> bus of the PC it's plugged into, and the primary purpose of the PC will
> be to process the data to & from this device, so having moderately high
> CPU usage requirements is not much of a concern.
>

I am no lawyer, but it my understanding that the Lattice reference
design is intended for use on Lattice devices. The license agreement
says something like: "for the sole purpose of programming Lattice
programmable logic devices."

If you use the Lattice PCI reference design, it sounds like you should
use the LatticeECP2 device or another Lattice FPGA, a list of which you
can find here:
http://www.latticesemi.com/products/fpga/index.cfm


Hope this helps.
Bart Borosky, Lattice

Antti wrote:
> > but do you mean that at lattice they have a downloadable pci ip
> > retargettable to any fpga? (i.e  rtl code?) if yes could put here the link?
> >
> > Antti Lukats ha scritto:
>
> sure get it here
http://www.latticesemi.com/products/intellectualproperty/referencedesigns/pcitarget32bit33mhz.cfm
> 
> 100% verilog source included!
> 
> Antti
> http://antti-brain.com