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Combining Schematic and VHDL code in Webpack 8.1 ??

Started by Per Jensen July 19, 2006
Hello!

I am a beginner in VHDL programming. i am programming an Xilinx XC9572XL 
at the moment, and i have so far used VHDL programming.

I am a little bit unsure, if i can combine VHDL and Shcematic, so a part 
of the circuit is described by Schematic, and another by VHDL. Is it 
possible, and how do i "bind" these things together ?? When i add a new 
source as an Schematic and compile, it only uses the VHDL file and 
ignore the Schematic-file..

Can somebody tell me how i do this, or give me a link to a site that 
descibes it ? I have looked at Xilinx' site, but found nothing...

Regards,
Per Jensen,
Demmark.
Hi Per Jensen,
All the schematics are converted to VHDL or Verilog (look at the
source's properties dialog).
You can see the generated HDL code by double-clicking the "View HDL
functional model" in the "Design Utilities" in the process window.
To add an instance of a schematic to an HDL code double-click on "View
HDL instantiation tamplate" in the "Design Utilities" in the process
window, copy, paste and modify the code to the destination module
(verilog) or architecture (VHDL).
To add an instance of a schematic to another schematic: close all
schematic windows, in the processes window double-click the process
"generate schematic symbol" in the "Design Utilities". than open a
schematics and in the categories window there will be a new category
with the path of your project as the name, enter this category and
choose the needed generted by you symbol.

I hope that this helped!

Per Jensen wrote:
> Hello! > > I am a beginner in VHDL programming. i am programming an Xilinx XC9572XL > at the moment, and i have so far used VHDL programming. > > I am a little bit unsure, if i can combine VHDL and Shcematic, so a part > of the circuit is described by Schematic, and another by VHDL. Is it > possible, and how do i "bind" these things together ?? When i add a new > source as an Schematic and compile, it only uses the VHDL file and > ignore the Schematic-file.. > > Can somebody tell me how i do this, or give me a link to a site that > descibes it ? I have looked at Xilinx' site, but found nothing... > > Regards, > Per Jensen, > Demmark.
GaLaKtIkUs=99 wrote:
> Hi Per Jensen, > All the schematics are converted to VHDL or Verilog (look at the > source's properties dialog). > You can see the generated HDL code by double-clicking the "View HDL > functional model" in the "Design Utilities" in the process window. > To add an instance of a schematic to an HDL code double-click on "View > HDL instantiation tamplate" in the "Design Utilities" in the process > window, copy, paste and modify the code to the destination module > (verilog) or architecture (VHDL). > To add an instance of a schematic to another schematic: close all > schematic windows, in the processes window double-click the process > "generate schematic symbol" in the "Design Utilities". than open a > schematics and in the categories window there will be a new category > with the path of your project as the name, enter this category and > choose the needed generted by you symbol. > > I hope that this helped! >
GaLaKtIkUs, I am trying to do exactly that! I have created a schematic in Xilinx WebPack 8.2 that I want to use as a building block in another schematic. However, I have these two schematics in separate projects. How do I import my building block into my larger project? Can I create a symbol library of my building blocks? Any assistance you could provide this newbie would be very much appreciated. Thanks, -Nevo