Hardware book like "Code Complete"?

Weng Tianxiang wrote:
> Hi Mike,
> Thank you for your response.
> Now what is the first value after system asynchronous reset for first
> loop?

Whatever the reset code says it is.
If there is no reset code, it might be a 'U'.
Check your simulation waveforms for exact answers.

        -- Mike Treseler

You can assignee an initial value when a variable or signal is
declared, e.g.,

signal mysig: std_logic := '0';

This will be the initial value when simulation starts.  According to
VHDL LRM, if there is no initial value, the first value defined in the
data type will be used.  Since std_logic is defined as ('U', 'X', '0',
...) in 1164 package.  The 'U' value (for uninitialized) will be the
default value.

Since the initial value cannot always be synthesized, this approach
should not be used in synthesis.  It is better to use an explicit reset
mechanism to initialize a sequential circuit.

Mike G.


Weng Tianxiang wrote:
> Hi Mike,
> Thank you for your response.
> Now what is the first value after system asynchronous reset for first
> loop?
>
> Thank you.
>
> Weng
>
> Mike Treseler wrote:
> > Weng Tianxiang wrote:
> >
> > > In the following statement:
> > >   var := (var - 1) mod var_limit;
> > > var is not assigned any value before it is used. var_limit is a
> > > constant, of course.
> > > Anything is wrong?
> >
> > No.
> > For simulation, the present value is used
> > to calculate and save the expression value.
> > For synthesis, this is infers a register to save
> > the value for the next process loop.
> > 
> >     -- Mike Treseler

On Fri, 28 Jul 2006 11:33:25 -0700, Mike Treseler
   <mike_treseler@comcast.net> wrote:
> BobG wrote:
>> I read the whole thread and no one recommended "The Art Of Electronics"
>> by Horowitz and Hill??
>
> That's more of an electronics book than an RTL book.

It _is_ an electronics book. There is one mention of RTL, but it's
'resistor-transistor logic'. Not quite the same thing.

A bientot
Paul
-- 
Paul Floyd                 http://paulf.free.fr (for what it's worth)
Surgery: ennobled Gerald.

Hi Mike,
Thank you.

Weng



mikegurche@yahoo.com wrote:
> You can assignee an initial value when a variable or signal is
> declared, e.g.,
>
> signal mysig: std_logic := '0';
>
> This will be the initial value when simulation starts.  According to
> VHDL LRM, if there is no initial value, the first value defined in the
> data type will be used.  Since std_logic is defined as ('U', 'X', '0',
> ...) in 1164 package.  The 'U' value (for uninitialized) will be the
> default value.
>
> Since the initial value cannot always be synthesized, this approach
> should not be used in synthesis.  It is better to use an explicit reset
> mechanism to initialize a sequential circuit.
>
> Mike G.
>
>
> Weng Tianxiang wrote:
> > Hi Mike,
> > Thank you for your response.
> > Now what is the first value after system asynchronous reset for first
> > loop?
> >
> > Thank you.
> >
> > Weng
> >
> > Mike Treseler wrote:
> > > Weng Tianxiang wrote:
> > >
> > > > In the following statement:
> > > >   var := (var - 1) mod var_limit;
> > > > var is not assigned any value before it is used. var_limit is a
> > > > constant, of course.
> > > > Anything is wrong?
> > >
> > > No.
> > > For simulation, the present value is used
> > > to calculate and save the expression value.
> > > For synthesis, this is infers a register to save
> > > the value for the next process loop.
> > > 
> > >     -- Mike Treseler

I almost always use integer subtypes for counters, so it would not
simulate as 'U'.  I used a simple example to show a point about
combinatorial vs registered logic, not about reset; you can code async
or sync reset for registers using variables the same way you do for
signals.

Andy


mikegurche@yahoo.com wrote:
> You can assignee an initial value when a variable or signal is
> declared, e.g.,
>
> signal mysig: std_logic := '0';
>
> This will be the initial value when simulation starts.  According to
> VHDL LRM, if there is no initial value, the first value defined in the
> data type will be used.  Since std_logic is defined as ('U', 'X', '0',
> ...) in 1164 package.  The 'U' value (for uninitialized) will be the
> default value.
>
> Since the initial value cannot always be synthesized, this approach
> should not be used in synthesis.  It is better to use an explicit reset
> mechanism to initialize a sequential circuit.
>
> Mike G.
>
>
> Weng Tianxiang wrote:
> > Hi Mike,
> > Thank you for your response.
> > Now what is the first value after system asynchronous reset for first
> > loop?
> >
> > Thank you.
> >
> > Weng
> >
> > Mike Treseler wrote:
> > > Weng Tianxiang wrote:
> > >
> > > > In the following statement:
> > > >   var := (var - 1) mod var_limit;
> > > > var is not assigned any value before it is used. var_limit is a
> > > > constant, of course.
> > > > Anything is wrong?
> > >
> > > No.
> > > For simulation, the present value is used
> > > to calculate and save the expression value.
> > > For synthesis, this is infers a register to save
> > > the value for the next process loop.
> > > 
> > >     -- Mike Treseler

Andy wrote:
> I almost always use integer subtypes for counters, so it would not
> simulate as 'U'.  

I prefer integers for counters also.
Up to 31 bits, that is :)

           -- Mike Treseler

KJ wrote:
> > Many hands make light work. Get a couple of dozen of
> > experienced designers, a bunch of proof reading fact
> > checkers and one decent editor and you  got yourself
> > an open source book writing project.
> >
> > Put it out on sourceforge for free and make it useful for any
> > digital designer at any stage in their career or hobby.Do
> > a really good job and it can become the "bible" of the
> > industry that everyone has in the library.
> >
> Certainly an interesting idea.
> >
> > Do we have the critical mass to pull something like this off?
> >
> Always a big question...the other important question is finding the
> 'leader' to prod this along to get it going in the first place.
>
> KJ
A few months ago a similar Idea was posted on an ASIC and Digital
design community at Orkut. The basic Idea was
a) To collect class notes/Presentation on a particular topic and expand
it to a book or
b) A person will come up with the book outline and others will submit
articles on specific topics and flesh it out
The final goal being to get a set of books on hardware design. You can
check the details at http://edaindia.com/books/

Regards
 H.H.I Tracy 
....

vijayvithal jahagirdar wrote:
> A few months ago a similar Idea was posted on an ASIC and Digital
> design community at Orkut. The basic Idea was
> a) To collect class notes/Presentation on a particular topic and expand
> it to a book or
> b) A person will come up with the book outline and others will submit
> articles on specific topics and flesh it out
> The final goal being to get a set of books on hardware design. You can
> check the details at http://edaindia.com/books/
> 
> Regards
>  H.H.I Tracy 

Why not go with Wikipedia? It's so easy for anyone to add to.
Just host the wikipedia software on some other server, if
Wikipedia's policies aren't satisfactory.

-Dave

David Ashley <dash@nowhere.net.dont.email.me> writes:

> vijayvithal jahagirdar wrote:
>> A few months ago a similar Idea was posted on an ASIC and Digital
>> design community at Orkut. The basic Idea was
>> a) To collect class notes/Presentation on a particular topic and expand
>> it to a book or
>> b) A person will come up with the book outline and others will submit
>> articles on specific topics and flesh it out
>> The final goal being to get a set of books on hardware design. You can
>> check the details at http://edaindia.com/books/
>
> Why not go with Wikipedia? It's so easy for anyone to add to.
> Just host the wikipedia software on some other server, if
> Wikipedia's policies aren't satisfactory.

One could use http://wikibooks.org or http://wikia.com/ for hosting.
I too think that such a book project is doomed if the hurdle for
contributing is too high.

Cheers,
  Colin

Colin Marquardt wrote:
> David Ashley <dash@nowhere.net.dont.email.me> writes:
> >
> > Why not go with Wikipedia? It's so easy for anyone to add to.
> > Just host the wikipedia software on some other server, if
> > Wikipedia's policies aren't satisfactory.
>
> One could use http://wikibooks.org or http://wikia.com/ for hosting.
> I too think that such a book project is doomed if the hurdle for
> contributing is too high.
>
> Cheers,
>   Colin

Most of the contributors to this thread seem to agree that writing a
Speciality book does not justify the effort that needs to be put in.
The reasons stated are
1> Small number of Digital designers.
2> Long time required to finish writing the book.

As an example suppose I decide to write a document on "VHDL/Verilog
coding style for Low Power mixed signal designs" which basically
collates the various material available on this topic in Public domain
and presents it in an easy to read and implement format. Out of the
estimated 10,000 Digital design engineers only a couple of hundreds
engineers (for e.g. those working on chips for handheld applications)
will actually find the book useful to the work at hand and will be
actually interested in buying the book. This makes the effort put in
writing the book commerically unviable.

Now suppose as a part of my normal work(either academic or otherwise) I
come up with a similar document which my funding organisation allows me
to put in public domain. I would rather prefer to put it as
is(ppt,word,pdf,ps,html etc.) and move on to the next pending work,
rather than rewrite the document in the format required by wiki.

I think in such a situation one of the following approach may be
suitable
1> Upload the document to my personal website and post the url to
usenet and other forums.
2> Upload the document to a common repository(Some place for electronic
documents similar to what CPAN is for Perl code or CTAN for tex macros)
say a sharepoint or a twiki or an interface similar to CPAN.

Collecting a set of similar articles, say on the topic of "digital
design in a low power mixed signal design" written by different authors
would give those 200 engineers working in this field a standard
reference. Due to the different formats and writing styles it would not
be a proper book but it can act as a loosely bound reference material

At a later date if this does turn out to be a hot topic and a demand
exists for a published text  then it should be possible to get the
proper permissions form the respective authors and cleanup the
formatting linearise the content and publish the book.

Regards
Vijay