Creating EDIF from Verilog, then using VHDL wrapper

Hi group, here's a question:

Can I synthesise a component described in Verilog, obtain an EDIF, then
write a VHDL wrapper around it so as to integrate it into a greater
VHDL project.

yours in ignorance,

Robin

Robin Bruce schrieb:

> Hi group, here's a question:
>
> Can I synthesise a component described in Verilog, obtain an EDIF, then
> write a VHDL wrapper around it so as to integrate it into a greater
> VHDL project.
>
> yours in ignorance,
>
> Robin

you should yes.
most of the tools allow any mix of verilog-vhdl, but you can also use
edif as interim format

antti

Robin

Coming from a similar direction is one of our TechiTips here
http://www.enterpoint.co.uk/techitips/Previous_TechiTips/techitips_increment_synth.html.
It is a little bit old now but the module build up approach described
is still applicable to mixed language application.

John Adair
Enterpoint Ltd.

Robin Bruce wrote:
> Hi group, here's a question:
>
> Can I synthesise a component described in Verilog, obtain an EDIF, then
> write a VHDL wrapper around it so as to integrate it into a greater
> VHDL project.
> 
> yours in ignorance,
> 
> Robin