2Khz clock signal from 50Hz main frequency with ADPLL

Hello everyone,

I would like to ask if it is possible to generate 2Khz clock signal
from 50Hz main frequency
using an ADPLL. I have tried SN297 circuit implementation, but couldn't
achieve it.

Many thanks in advance,

Rasit

Phase-Locked Loops : Design, Simulation, and Applications (Professional 
Engineering) (Hardcover)
by Roland E. Best
Chapter 6.
HTH, Syms.
"raso" <rasit.sahin@yahoo.co.uk> wrote in message 
news:1153823652.202609.67390@m79g2000cwm.googlegroups.com...
> Hello everyone,
>
> I would like to ask if it is possible to generate 2Khz clock signal
> from 50Hz main frequency
> using an ADPLL. I have tried SN297 circuit implementation, but couldn't
> achieve it.
>
> Many thanks in advance,
>
> Rasit
> 

On a sunny day (25 Jul 2006 03:34:12 -0700) it happened "raso"
<rasit.sahin@yahoo.co.uk> wrote in
<1153823652.202609.67390@m79g2000cwm.googlegroups.com>:

>Hello everyone,
>
>I would like to ask if it is possible to generate 2Khz clock signal
>from 50Hz main frequency

It is important to filter the mains frequency first from spikes and the like.
Then perhaps create a pulse at zero crossing to drive the PLL.

Dear Jan,

This part is not a problem at all.

What I need to do is to keep the number of 2Khz pulses
same as the main 50Hz changes. In perfect condition
there are fourty 2Khz cycles within one 50Hz period  (20ms/500us).
When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also
chance accordingly to stay in lock.

My system clock is 60MHz. I implemented a JK phase detector, a
K-counter and a DCO in order to generate 2KHz pulses and this system
operates at system clock. The
output locks to exact 50Hz very quickly (fed from signal generator),
but when I change the reference clock to, lets say, 50.1Hz it starts
drifting.

Any help appreciated.

Many thanks,
Rasit

Jan Panteltje wrote:
> On a sunny day (25 Jul 2006 03:34:12 -0700) it happened "raso"
> <rasit.sahin@yahoo.co.uk> wrote in
> <1153823652.202609.67390@m79g2000cwm.googlegroups.com>:
>
> >Hello everyone,
> >
> >I would like to ask if it is possible to generate 2Khz clock signal
> >from 50Hz main frequency
>
> It is important to filter the mains frequency first from spikes and the like.
> Then perhaps create a pulse at zero crossing to drive the PLL.

On a sunny day (25 Jul 2006 07:45:49 -0700) it happened "raso"
<rasit.sahin@yahoo.co.uk> wrote in
<1153838749.560177.182570@b28g2000cwb.googlegroups.com>:

>Dear Jan,
>
>This part is not a problem at all.
>
>What I need to do is to keep the number of 2Khz pulses
>same as the main 50Hz changes.

You mean per 50 Hz period.

>In perfect condition
>there are fourty 2Khz cycles within one 50Hz period  (20ms/500us).
>When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also
>chance accordingly to stay in lock.

Yes.

>My system clock is 60MHz. I implemented a JK phase detector, a
>K-counter and a DCO in order to generate 2KHz pulses and this system
>operates at system clock. The
>output locks to exact 50Hz very quickly (fed from signal generator),
>but when I change the reference clock to, lets say, 50.1Hz it starts
>drifting.

Well, I dunno, but I did something like that with 4046 PLL in the 1980ties,
divide the 2 kHz to 100 Hz, compare with 100Hz zero crossing derived filtered
mains pulses.
The issue is the loop filter (lock in range and stability) and loop gain.
You need to read up on PLL design perhaps.

All I know :-)

raso schrieb:

> What I need to do is to keep the number of 2Khz pulses
> same as the main 50Hz changes. In perfect condition
> there are fourty 2Khz cycles within one 50Hz period  (20ms/500us).
> When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also
> chance accordingly to stay in lock.

Sure, otherwise it wouldnt be a PLL.
But remember, 0.1 Hz change from 50 Hz is 1/500 = 2 promille = 2000 ppm.
Is the pull range of the PLL wide enough?
Try changes of +/-50 ppm and see how it works. Than increase the deviation.

Regards
Falk

raso wrote:

>Hello everyone,
>
>I would like to ask if it is possible to generate 2Khz clock signal
>from 50Hz main frequency
>using an ADPLL. I have tried SN297 circuit implementation, but couldn't
>achieve it.
>  
>
The 74LS297 has a VERY narrow lock range, compared to traditional
analog PLL's.  It is generally a fraction of a percent, but I think there
is a setting that gives you a couple percent range.  It works fine for
syncing between a data source running on one xtal clock, from another
xtal clock.  You would need a digital clock (quartz crystal) that is at
some multiple of 50 Hz (not too hard).  Then, you'd need a couple of
long counter chains to do the divide down.

Are you using an HLL library version of the 74LS297 circuit?  If so,
where did you get it?  I happen to use the real TI chip in one device I
built, and a synthesizable version might be good to know about.

Jon

raso wrote:
> Dear Jan,
> 
> This part is not a problem at all.
> 
> What I need to do is to keep the number of 2Khz pulses
> same as the main 50Hz changes. In perfect condition
> there are fourty 2Khz cycles within one 50Hz period  (20ms/500us).
> When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also
> chance accordingly to stay in lock.
> 
> My system clock is 60MHz. I implemented a JK phase detector, a
> K-counter and a DCO in order to generate 2KHz pulses and this system
> operates at system clock. The
> output locks to exact 50Hz very quickly (fed from signal generator),
> but when I change the reference clock to, lets say, 50.1Hz it starts
> drifting.

  You will also get phase jitter on Mains 50Hz references, as well as
the frequency drifts - in most countries they try and keep the number of
cycles in a day correct, for operating clocks.
  So, you need to realise this will always be a historical-fit based 
lock. What you decide for the next mains cycle might not actually be 
correct, but you can make a best guess based on the pevious ones.

With MHz to burn, and FPGA, why not use a
Freqency Counter/IndexCounter/LoadableDivider, with a slow tracking 
Up/down coounter on the index.
It can be 100% digital, and the tracking speed becomes the PLL-LPF.

Looks like you need to track 1% dF, keeping a nominal 40 clocks / cycle,
with a possible divide of 30,000 (!), that should be do-able :)

Many mains systems use zero crossing phase lock, and do not bother about 
the small freqency variations.

-jg

Hi Jon,

Falk Brunner sent me his VHDL implementation of 74LS297. I modified it
so that K-counter and I/D counter (DCO) run at system clock which is
30MHz.

The system has following blocks;

- The first component is an JKFF based phase detector.
- Then, there is a K-counter operating at 30MHz. With 30MHz clock, a
full 50Hz
period means M=30e6/50=600000 ticks. For minimum jitter, modulus of K
counter is set M/2 which is 300000. The borrow pulse decreases the
modulus of I/D counter (2KHz DCO) while carry pulse increases it by 1.
So in locked condition, it generates 1 carry and 1 borrow pulse within
one 50Hz period and they cancel each other.
- I/D counter is a DCO (modulus counter). It operates  at 30MHz. When
it is locked to 50Hz it has modulus of 15000. When 50Hz changes, the
borrow and carry pulses should adjust the modulus of I/D counter (carry
pulse increases the modulus by 1, and borrow decreases it by 1). By
this way, period of 2kHz pulses is adjusted according to 50Hz input.
- N-Counter which devides 2Khz clock by 40.

The only parameter that I can play with is the modulus of K counter.

I can't use direct implementation of 74LS297. Because, it syncronises
f_in and f_out by inserting or deleting 2KHz pulses (I/D pulses). I
can't tolerate inserting or deleting 2KHz pulses. It has to keep the
number of 2kHz pulses as 40 in each 50Hz period.

Isa

Jon Elson wrote:
> raso wrote:
>
> >Hello everyone,
> >
> >I would like to ask if it is possible to generate 2Khz clock signal
> >from 50Hz main frequency
> >using an ADPLL. I have tried SN297 circuit implementation, but couldn't
> >achieve it.
> >
> >
> The 74LS297 has a VERY narrow lock range, compared to traditional
> analog PLL's.  It is generally a fraction of a percent, but I think there
> is a setting that gives you a couple percent range.  It works fine for
> syncing between a data source running on one xtal clock, from another
> xtal clock.  You would need a digital clock (quartz crystal) that is at
> some multiple of 50 Hz (not too hard).  Then, you'd need a couple of
> long counter chains to do the divide down.
>
> Are you using an HLL library version of the 74LS297 circuit?  If so,
> where did you get it?  I happen to use the real TI chip in one device I
> built, and a synthesizable version might be good to know about.
> 
> Jon

Dear Jim,

Could you please explain your idea below?

>> With MHz to burn, and FPGA, why not use a
>> Freqency Counter/IndexCounter/LoadableDivider, with a slow tracking
>> Up/down coounter on the index.
>> It can be 100% digital, and the tracking speed becomes the PLL-LPF.

Many thanks,
Isa

Jim Granville wrote:
> raso wrote:
> > Dear Jan,
> >
> > This part is not a problem at all.
> >
> > What I need to do is to keep the number of 2Khz pulses
> > same as the main 50Hz changes. In perfect condition
> > there are fourty 2Khz cycles within one 50Hz period  (20ms/500us).
> > When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also
> > chance accordingly to stay in lock.
> >
> > My system clock is 60MHz. I implemented a JK phase detector, a
> > K-counter and a DCO in order to generate 2KHz pulses and this system
> > operates at system clock. The
> > output locks to exact 50Hz very quickly (fed from signal generator),
> > but when I change the reference clock to, lets say, 50.1Hz it starts
> > drifting.
>
>   You will also get phase jitter on Mains 50Hz references, as well as
> the frequency drifts - in most countries they try and keep the number of
> cycles in a day correct, for operating clocks.
>   So, you need to realise this will always be a historical-fit based
> lock. What you decide for the next mains cycle might not actually be
> correct, but you can make a best guess based on the pevious ones.
>
> With MHz to burn, and FPGA, why not use a
> Freqency Counter/IndexCounter/LoadableDivider, with a slow tracking
> Up/down coounter on the index.
> It can be 100% digital, and the tracking speed becomes the PLL-LPF.
>
> Looks like you need to track 1% dF, keeping a nominal 40 clocks / cycle,
> with a possible divide of 30,000 (!), that should be do-able :)
>
> Many mains systems use zero crossing phase lock, and do not bother about
> the small freqency variations.
> 
> -jg