How to phase align a 10MHz clock using V4LX60 DCM

Hello,
    I am now working with new board based on ARM processor which is
pluged on top of V4LX60 based board from avnet. But after the ARM board
is manufactured it is observed that the clock from the ARM is delayed
compared to the other signals. Since redesign of the board is not
possible i thought to advance the clock by 4ns using the DCM on the V4
board.
    But the problem is the clock signal is only 10MHz frequency. Thus
it is outside the  frequency range (input clock) of the DCM if i am
using the CLK0 output. Thus it is possible to use only the CLKFX
output. But the minimum output frequency is 32MHz. Thus i thought to
use two DCMs. One to multiply the input clock with 10 and will do a
phase shift of 4ns. Then this will be divided by another DCM which will
divide by 10 to get a phase advanced 10MHz frequency.
    But the problem observed is that the input 10MHz and the multiplied
100Mhz are phase aligned also the input to second DCM and the output
10MHz are also aligned. The First input and the output of the second
DCM is not showing any relation ship.
     How can i tackle this problem

When you multiply a clock and then divide it, there is no common
phase relationship of the output unless you reference the original
signal.  I would suggest sampling the input clock using a flip-flop
clocked by the 10x clock.  The output of this flip-flop should have
a constant (somewhat delayed) phase relationship to the original.
Additional 10x clock delays can then be added to adjust the clock
to the desired phase.

subint wrote:
> Hello,
>     I am now working with new board based on ARM processor which is
> pluged on top of V4LX60 based board from avnet. But after the ARM board
> is manufactured it is observed that the clock from the ARM is delayed
> compared to the other signals. Since redesign of the board is not
> possible i thought to advance the clock by 4ns using the DCM on the V4
> board.
>     But the problem is the clock signal is only 10MHz frequency. Thus
> it is outside the  frequency range (input clock) of the DCM if i am
> using the CLK0 output. Thus it is possible to use only the CLKFX
> output. But the minimum output frequency is 32MHz. Thus i thought to
> use two DCMs. One to multiply the input clock with 10 and will do a
> phase shift of 4ns. Then this will be divided by another DCM which will
> divide by 10 to get a phase advanced 10MHz frequency.
>     But the problem observed is that the input 10MHz and the multiplied
> 100Mhz are phase aligned also the input to second DCM and the output
> 10MHz are also aligned. The First input and the output of the second
> DCM is not showing any relation ship.
>      How can i tackle this problem

Gabor wrote:
> When you multiply a clock and then divide it, there is no common
> phase relationship of the output unless you reference the original
> signal.  I would suggest sampling the input clock using a flip-flop
> clocked by the 10x clock.  The output of this flip-flop should have
> a constant (somewhat delayed) phase relationship to the original.
> Additional 10x clock delays can then be added to adjust the clock
> to the desired phase.
>
>
Hi I am Subins collegue,
  What we are trying to do is advance the input clock by 4 to 6 ns not
to delay it.

vssumesh wrote:

>Gabor wrote:
>  
>
>>When you multiply a clock and then divide it, there is no common
>>phase relationship of the output unless you reference the original
>>signal.  I would suggest sampling the input clock using a flip-flop
>>clocked by the 10x clock.  The output of this flip-flop should have
>>a constant (somewhat delayed) phase relationship to the original.
>>Additional 10x clock delays can then be added to adjust the clock
>>to the desired phase.
>>
>>
>>    
>>
>Hi I am Subins collegue,
>  What we are trying to do is advance the input clock by 4 to 6 ns not
>to delay it.
>
>  
>
pretty much the same thing, if you are considering that the delayed 
version, it's an "early" version against the next transition..., 
otherwise just wait for soeone to invent a time machine.
Aurash

-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Aurelian Lazarut wrote:
> vssumesh wrote:
>
> >Gabor wrote:
> >
> >
> >>When you multiply a clock and then divide it, there is no common
> >>phase relationship of the output unless you reference the original
> >>signal.  I would suggest sampling the input clock using a flip-flop
> >>clocked by the 10x clock.  The output of this flip-flop should have
> >>a constant (somewhat delayed) phase relationship to the original.
> >>Additional 10x clock delays can then be added to adjust the clock
> >>to the desired phase.
> >>
> >>
> >>
> >>
> >Hi I am Subins collegue,
> >  What we are trying to do is advance the input clock by 4 to 6 ns not
> >to delay it.
> >
> >
> >
> pretty much the same thing, if you are considering that the delayed
> version, it's an "early" version against the next transition...,
> otherwise just wait for soeone to invent a time machine.
> Aurash

Snort

The other possibility is to delay all the other signals on 1 metre of
FR4. That'll advance the clock relatively by 6 nS ;)

Cheers

PeteS


>
> --
>  __
> / /\/\ Aurelian Lazarut
> \ \  / System Verification Engineer
> / /  \ Xilinx Ireland
> \_\/\/
>  
> phone:	353 01 4032639
> fax:	353 01 4640324