Programmable pulse generator

Hi All,

I'm trying to develop a programmable pulse generator, essentially a
single pulse of variable width repeated at a given rate. I posted a
similar question a few weeks ago on sci.elec.design and someone
suggested that this would make a nice CPLD project. As I'm keen to
learn about programmable logic devices I decided to buy a development
kit (Altera 7000 series) and try implementing the pulse generator.

My ideal specification would be pulse widths from 10ns to 10us
incremented in 10ns steps at repetition rates between 1 to 10 kHz. The
evaluation board has a 25MHz clock so I'm limited to 40ns increments
but that's ok for now.

I've been playing around with various counters etc but am struggling
to create anything useful, would be great if someone more experienced
could give me a few hints!?

Thanks,

Jim W

Użytkownik jimwalsh142@hotmail.com napisał:
> Hi All,
> 
> I'm trying to develop a programmable pulse generator, essentially a
> single pulse of variable width repeated at a given rate. I posted a
> similar question a few weeks ago on sci.elec.design and someone
> suggested that this would make a nice CPLD project. As I'm keen to
> learn about programmable logic devices I decided to buy a development
> kit (Altera 7000 series) and try implementing the pulse generator.
> 
> My ideal specification would be pulse widths from 10ns to 10us
> incremented in 10ns steps at repetition rates between 1 to 10 kHz. The
> evaluation board has a 25MHz clock so I'm limited to 40ns increments
> but that's ok for now.
> 
> I've been playing around with various counters etc but am struggling
> to create anything useful, would be great if someone more experienced
> could give me a few hints!?
> 
> Thanks,
> 
> Jim W
> 

Hi,

I can do  it for you.
Let me know how you want to set parameters - parallel interface to 
microcontroller , microprocessor or serial controll ?


Adam

jimwalsh142@hotmail.com wrote:

> I'm trying to develop a programmable pulse generator, essentially a
> single pulse of variable width repeated at a given rate. 

I would recommend a synchronous design
using clock enabled counters.

The RTL example "clk enabled counters" here:

  http://home.comcast.net/~mike_treseler/

is not a pulse generator, but
it does demonstrate square waves of
three frequencies.

        -- Mike Treseler

<jimwalsh142@hotmail.com> wrote in message 
news:1154471886.472858.324360@s13g2000cwa.googlegroups.com...
> Hi All,
>
> I'm trying to develop a programmable pulse generator, essentially a
> single pulse of variable width repeated at a given rate. I posted a
> similar question a few weeks ago on sci.elec.design and someone
> suggested that this would make a nice CPLD project. As I'm keen to
> learn about programmable logic devices I decided to buy a development
> kit (Altera 7000 series) and try implementing the pulse generator.
>
> My ideal specification would be pulse widths from 10ns to 10us
> incremented in 10ns steps at repetition rates between 1 to 10 kHz. The
> evaluation board has a 25MHz clock so I'm limited to 40ns increments
> but that's ok for now.
>
> I've been playing around with various counters etc but am struggling
> to create anything useful, would be great if someone more experienced
> could give me a few hints!?
>
> Thanks,
>
> Jim W

If you want to do it yourself, are you doing schematic, Verilog, or VHDL?
For the guts you just want a counter that runs from one to your period-1 
(after which it rolls back to 0) and a comparator for the number of cycles 
for your output pulse high.  The registered comparator output give you a 
nice, clean, programmed pulse.

If you had a 100 MHz source, 10 us would require a count to at least 999 or 
10 bits.  This 10-bit counter also needs two 10-bit values, one for the 
period and one for the high width.  The 10-bit comparator should implement 
nicely in the CPLD.  The two 10-bit values need to be written into the CPLD 
in some form.  If your load signal is asynchronous, be aware that changing 
the setting may present an unexpected glitch or runt pulse.  Let us know if 
you need to avoid a single bad pulse when changing settings.

Also, do you have more than 32 Macrocells to work with and want more bells 
and whistles? 

jimwalsh142@hotmail.com wrote:
> Hi All,
> 
> I'm trying to develop a programmable pulse generator, essentially a
> single pulse of variable width repeated at a given rate. I posted a
> similar question a few weeks ago on sci.elec.design and someone
> suggested that this would make a nice CPLD project. As I'm keen to
> learn about programmable logic devices I decided to buy a development
> kit (Altera 7000 series) and try implementing the pulse generator.
> 
> My ideal specification would be pulse widths from 10ns to 10us
> incremented in 10ns steps at repetition rates between 1 to 10 kHz. The
> evaluation board has a 25MHz clock so I'm limited to 40ns increments
> but that's ok for now.
> 
> I've been playing around with various counters etc but am struggling
> to create anything useful, would be great if someone more experienced
> could give me a few hints!?

Where are you struggling ?

For a single pulse, you need a saturating, Reloadable counter - one that 
loads, counts, then stops when it hits some limit - Commonly 0000.
10us from 40ns is appx 8 bit counter. ( 10-12 bits if you load with BCD 
thumbwheels)

  For linear frequecy rep-rate, that's not quite as simple as normal /N 
is a 1/X curve.
  Choices are a small ROM ( OK for a few Freqs), or a Rate Multiplier or 
DDS frequency scheme.
  With a Rate Multiplier, run it from max Clk, and post-scale to the < 
10KHz re-trigger frequency you want, to reduce jitter.

  Do you mean 1KHz to 10Khz, or 1Hz to 10Khz ? - former is one decade of 
Prog Fo, doable in 4 bits of RateMult, latter is 4 decades, so needs
appx 14 bits binary, or 20 bits if you load with BCD thumbwheels.
  10Khz to 25Mhz of postscale is ~11 bits binary.

Another pulse-generator approach, is to define the ON and OFF times, 
then you have just one timing chain, which is a reloadable counter, from 
two alternating set-values.

That's simple logic, but more set-point wires, or you could choose to 
compile-in the settings, and use the ISP cable to set. [ Smaller CPLD 
and less wires ]

-jg

John_H wrote:
>

A perhaps better approach is to use a loadable down-counter that is one 
bit wider than your maximum count.  That way, the terminal count is just 
the MSB of the counter, and it can be used to disable the count as well. 
  This eliminates the comparator.

A DDS can be used to get a programmable rate that is not an integer 
multiple of the clock frequency and that has a linear relationship 
between the program value and the output frequency.  The DDS is 
basically just an accumulator to which a fixed increment is added on 
each clock cycle. The square-wave output is taken from the MSB of the 
accumulator. (It will have jitter of up to a clock cycle depending on 
the increment value).

Jim Granville wrote:
> jimwalsh142@hotmail.com wrote:
> > Hi All,
> >
> > I'm trying to develop a programmable pulse generator, essentially a
> > single pulse of variable width repeated at a given rate. I posted a
> > similar question a few weeks ago on sci.elec.design and someone
> > suggested that this would make a nice CPLD project. As I'm keen to
> > learn about programmable logic devices I decided to buy a development
> > kit (Altera 7000 series) and try implementing the pulse generator.
> >
> > My ideal specification would be pulse widths from 10ns to 10us
> > incremented in 10ns steps at repetition rates between 1 to 10 kHz. The
> > evaluation board has a 25MHz clock so I'm limited to 40ns increments
> > but that's ok for now.
> >
> > I've been playing around with various counters etc but am struggling
> > to create anything useful, would be great if someone more experienced
> > could give me a few hints!?
>
> Where are you struggling ?
>
> For a single pulse, you need a saturating, Reloadable counter - one that
> loads, counts, then stops when it hits some limit - Commonly 0000.
> 10us from 40ns is appx 8 bit counter. ( 10-12 bits if you load with BCD
> thumbwheels)
>
>   For linear frequecy rep-rate, that's not quite as simple as normal /N
> is a 1/X curve.
>   Choices are a small ROM ( OK for a few Freqs), or a Rate Multiplier or
> DDS frequency scheme.
>   With a Rate Multiplier, run it from max Clk, and post-scale to the <
> 10KHz re-trigger frequency you want, to reduce jitter.
>
>   Do you mean 1KHz to 10Khz, or 1Hz to 10Khz ? - former is one decade of
> Prog Fo, doable in 4 bits of RateMult, latter is 4 decades, so needs
> appx 14 bits binary, or 20 bits if you load with BCD thumbwheels.
>   10Khz to 25Mhz of postscale is ~11 bits binary.
>
> Another pulse-generator approach, is to define the ON and OFF times,
> then you have just one timing chain, which is a reloadable counter, from
> two alternating set-values.
>
> That's simple logic, but more set-point wires, or you could choose to
> compile-in the settings, and use the ISP cable to set. [ Smaller CPLD
> and less wires ]
>
> -jg

Thanks for all the useful replies!

I think I need to clarify my setup... I have a small microcontroller
that generates a PWM signal and I was planning to use this as the
repetition rate. Also attached to the uC is an LCD and keypad to enable
the user to enter the pulse width and rep rate. I'm ok with that and
it works well.

At the minute I'm using a Altera Max epm7128slc84-10 which has 128
macrocells. I'm really new to all this so I have been using the
schematic design entry tool. So far I have managed to use two 74160
decade programmable counters to divide my clock, the counters are
controlled by the microprocessor. This approach fails because the duty
cycle of the divided clock isn't 50% and I still don't know how to
get a single pulse from the train of pulses?

By the way, my first approach was to use a Pic & DDS I put the idea on
hold as I can't make PCB's and the DDS is surface mount! Also I'm
learning much more doing this via CPLD as I've never used anything
like it before.

Thanks for the help,

Jim W.

jimwalsh142@hotmail.com wrote:
<snip>
> Thanks for all the useful replies!
> 
> I think I need to clarify my setup... I have a small microcontroller
> that generates a PWM signal and I was planning to use this as the
> repetition rate. Also attached to the uC is an LCD and keypad to enable
> the user to enter the pulse width and rep rate. I'm ok with that and
> it works well.

OK, so this is a uC augmented by CPLD, which is a good combination.

> 
> At the minute I'm using a Altera Max epm7128slc84-10 which has 128
> macrocells. I'm really new to all this so I have been using the
> schematic design entry tool. So far I have managed to use two 74160
> decade programmable counters to divide my clock, the counters are
> controlled by the microprocessor. This approach fails because the duty
> cycle of the divided clock isn't 50% and I still don't know how to
> get a single pulse from the train of pulses?

You need to make a 'digital monostable' - start the counter on an edge
from the uC PWM, and then stop, and hold until the next trigger edge, 
after NNN clock cycles.

Taking your 74160, you need a JK FF, driving the 160.ClockEnable
Setup an edge detector ( one clock pulse wide ) from the PWM, and The JK 
FF is set on this, the same one-clock pulse does the SyncLoad of the 
160s. Then the terminal count from the 160, clears the JK FF, which
holds everything paused, until the next Edge.
The JK ff gives a variable width wide pulse.

Use a common clock for the PLD and uC, to avoid clock race conditions.

> 
> By the way, my first approach was to use a Pic & DDS I put the idea on
> hold as I can't make PCB's and the DDS is surface mount! Also I'm
> learning much more doing this via CPLD as I've never used anything
> like it before.
> 
> Thanks for the help,
> 
> Jim W.
> 

Ray Andraka wrote:
> John_H wrote:

> A DDS can be used to get a programmable rate that is not an integer
> multiple of the clock frequency and that has a linear relationship
> between the program value and the output frequency.  The DDS is
> basically just an accumulator to which a fixed increment is added on
> each clock cycle. The square-wave output is taken from the MSB of the
> accumulator. (It will have jitter of up to a clock cycle depending on
> the increment value).

I prefer Bresenhams algorithm for frequency generation.
The N-bit accumulator has a frequency error of up to 1/2^N.
Bresenhams algorithm is exact for the question "generate N pulses in M
clock cycles". I also has minimum jitter (up to half a clock cycle).
The hardware implementation is simple and small.

Kolja Sulimma

Kolja Sulimma wrote:
> Ray Andraka wrote:
> > John_H wrote:
>
> > A DDS can be used to get a programmable rate that is not an integer
> > multiple of the clock frequency and that has a linear relationship
> > between the program value and the output frequency.  The DDS is
> > basically just an accumulator to which a fixed increment is added on
> > each clock cycle. The square-wave output is taken from the MSB of the
> > accumulator. (It will have jitter of up to a clock cycle depending on
> > the increment value).
>
> I prefer Bresenhams algorithm for frequency generation.
> The N-bit accumulator has a frequency error of up to 1/2^N.
> Bresenhams algorithm is exact for the question "generate N pulses in M
> clock cycles". I also has minimum jitter (up to half a clock cycle).
> The hardware implementation is simple and small.
>
> Kolja Sulimma

I have't heard of that... could you post some links?

Thanks,

JW