MicroBlaze SPI interrupts

Hello All,

I'm on a project which has ballooned in scope such that it calls for
implementing the MicroBlaze (originally it called for a straight
forward PicoBlaze, but that's a long story ...)

I have successfully created custom peripherals and have implemented the
code to control them from my device MMI. Thus, I'm mildly savvy wrt
Xilinx EDK. However, I cannot get my SPI (EEPROM) peripheral to play
nice-nice with the rest of the project.

The transfer will begin successfully via  XSpi_Transfer(...) but SS
(CS) never de-asserts. The only work around I have come up with is
XSpi_Reset(...), but that is pretty ugly and will more than likely
present problems further down the road. I have a suspicion that I am
not initalizing the SPI status handler or the interrupt controller
correctly. I'd be the first to admit that I haven't dealt with
interrupts since a really crappy lab on them in undergrad ....

I apologize in advance if I haven't furnished enough information to
help me. I'm more of a squishy analog hardware type. Any advice or
application notes that are applicable would be greatly appreciated.

Thanks,
Matt

fbs.consulting@gmail.com schrieb:

> Hello All,
>
> I'm on a project which has ballooned in scope such that it calls for
> implementing the MicroBlaze (originally it called for a straight
> forward PicoBlaze, but that's a long story ...)
>
> I have successfully created custom peripherals and have implemented the
> code to control them from my device MMI. Thus, I'm mildly savvy wrt
> Xilinx EDK. However, I cannot get my SPI (EEPROM) peripheral to play
> nice-nice with the rest of the project.
>
> The transfer will begin successfully via  XSpi_Transfer(...) but SS
> (CS) never de-asserts. The only work around I have come up with is
> XSpi_Reset(...), but that is pretty ugly and will more than likely
> present problems further down the road. I have a suspicion that I am
> not initalizing the SPI status handler or the interrupt controller
> correctly. I'd be the first to admit that I haven't dealt with
> interrupts since a really crappy lab on them in undergrad ....
>
> I apologize in advance if I haven't furnished enough information to
> help me. I'm more of a squishy analog hardware type. Any advice or
> application notes that are applicable would be greatly appreciated.
>
> Thanks,
> Matt

see at end. defenetly working code that reads ST serial flash ID code
using OPB_SPI
no interrupts though, but you should be able to use the code to verify
the basic SPI
operations

Antti




// SPI
Xuint16 Control;
Xuint8 SpiBuffer[32];
int NumBytesSent;
int NumBytesRcvd;


void SPI_init() {
    XSpi_mSetSlaveSelectReg(SPI_BASEADDR, 0xFFFFFFFF);
    Control =
	XSP_CR_MANUAL_SS_MASK | XSP_CR_MASTER_MODE_MASK | XSP_CR_ENABLE_MASK |
XSP_CR_TRANS_INHIBIT_MASK;
    XSpi_mSetControlReg(SPI_BASEADDR, Control);
}


int SPI_transfer(int count) {
	//

	int i;

    NumBytesSent = 0;
    NumBytesRcvd = 0;

    /*
     * Set up the device in loopback mode and enable master mode
     */
    XSpi_mSetSlaveSelectReg(SPI_BASEADDR, 0xFFFFFFFF);

    /*
     * Fill up the transmitter with data, assuming the receiver can
hold
     * the same amount of data.
     */
	for (i=0;i<count;i++) {
		XSpi_mSendByte(SPI_BASEADDR, SpiBuffer[i]);
	}

    /*
     * Enable the device
     */
    XSpi_mSetSlaveSelectReg(SPI_BASEADDR, 0xFFFFFFFD);  // flash

    Control &= ~XSP_CR_TRANS_INHIBIT_MASK;
    XSpi_mSetControlReg(SPI_BASEADDR, Control);

    /*
     * Wait for the transmit FIFO to transition to empty before
checking
     * the receive FIFO, this prevents a fast processor from seeing the
     * receive FIFO as empty
     */

    while (!(XSpi_mGetStatusReg(SPI_BASEADDR) & XSP_SR_TX_EMPTY_MASK));

    /*
     * Transmitter is full, now receive the data just looped back until
     * the receiver is empty.
     */
    while ((XSpi_mGetStatusReg(SPI_BASEADDR) & XSP_SR_RX_EMPTY_MASK) ==
0)
    {
        SpiBuffer[NumBytesRcvd++] = XSpi_mRecvByte(SPI_BASEADDR);
    }


    /*
     * If no data was sent or the data that was sent was not received,
     * then return an error
     */

//    Control &= ~XSP_CR_ENABLE_MASK;
//    XSpi_mSetControlReg(SPI_BASEADDR, Control);

    Control |= XSP_CR_TRANS_INHIBIT_MASK;
    XSpi_mSetControlReg(SPI_BASEADDR, Control);
    return 0;
}

int SPI_query() {
	// READ ID Command:
	SpiBuffer[0] = 0x9F;
	SPI_transfer(4);
	xil_printf("\n\rFlash Id: %2X%2X%2X\n\r",
SpiBuffer[1],SpiBuffer[2],SpiBuffer[3]);
}