DDR Controller

Hi,
I am to build a fpga system that captures data from external signals
and store it to DDR, also after the capture data must be transferred to
the PC via PCI bus via DMA or so.
So this is a CAPTURE-to-DDR  DDR-to-PCI... How is this sytem
implemented?

yy wrote:
> Hi,
> I am to build a fpga system that captures data from external signals
> and store it to DDR, also after the capture data must be transferred to
> the PC via PCI bus via DMA or so.
> So this is a CAPTURE-to-DDR  DDR-to-PCI... How is this sytem
> implemented?

You've already stated the requirements (albeit in a vague way). Tighten
up the definition and any decent designer would be able to come up with
an implementation. If you are to build it, you'll learn nothing if you
don't try to figure out the implementation [truly a core skill in
design!] yourself.

Cheers

PeteS

Ayon kay PeteS:
> yy wrote:
> > Hi,
> > I am to build a fpga system that captures data from external signals
> > and store it to DDR, also after the capture data must be transferred to
> > the PC via PCI bus via DMA or so.
> > So this is a CAPTURE-to-DDR  DDR-to-PCI... How is this sytem
> > implemented?
>
> You've already stated the requirements (albeit in a vague way). Tighten
> up the definition and any decent designer would be able to come up with
> an implementation. If you are to build it, you'll learn nothing if you
> don't try to figure out the implementation [truly a core skill in
> design!] yourself.
>
> Cheers
>
> PeteS


Hi PeteS,
 I will elaborate so that my concept will be clear.
First of all the idea is for the PCI to read/write data from multiple
DDR (with DDR controller interface).
With the PCI Master core connected to a DMA Engine and FIFO buffer that
is connected to the 'DDR SDRAM Controller Interface' that is connected
to the DDR Module itself, and if possible be connected to other DDR
Controller Interface, can that be possible? such that when I access
BAR1, for example i'm accessing DDR1 Interface, BAR2 for DDR2 Interface
etc., along with this a Custom logic1 that use DDR1as its data must be
able to access the same 'DDR Controller Interface1' , Custom Logic2
that use DDR2 as its data must be able to access the same DDR
Controller Interface2, etc.
In short is it possible to have seperate port for a DDR Controller
Interface connected to a single DDR module to have dual access 'port',
one for the PCI-DMA Engine and one for the Custom Logic(but not both at
the same time)? 

Regards,
yy

yy a �crit :
[...]
> With the PCI Master core connected to a DMA Engine and FIFO buffer that
> is connected to the 'DDR SDRAM Controller Interface' that is connected
> to the DDR Module itself, and if possible be connected to other DDR
> Controller Interface, can that be possible? such that when I access
> BAR1, for example i'm accessing DDR1 Interface, BAR2 for DDR2 Interface
> etc., along with this a Custom logic1 that use DDR1as its data must be
> able to access the same 'DDR Controller Interface1' , Custom Logic2
> that use DDR2 as its data must be able to access the same DDR
> Controller Interface2, etc.


Hi
There's really *nothing* fancy here.
Imagine a system with a microprocessor (with integrated cache), DDR and 
a PCI bus...

Nicolas

Ayon kay Nicolas Matringe:
> yy a =E9crit :
> [...]
> > With the PCI Master core connected to a DMA Engine and FIFO buffer that
> > is connected to the 'DDR SDRAM Controller Interface' that is connected
> > to the DDR Module itself, and if possible be connected to other DDR
> > Controller Interface, can that be possible? such that when I access
> > BAR1, for example i'm accessing DDR1 Interface, BAR2 for DDR2 Interface
> > etc., along with this a Custom logic1 that use DDR1as its data must be
> > able to access the same 'DDR Controller Interface1' , Custom Logic2
> > that use DDR2 as its data must be able to access the same DDR
> > Controller Interface2, etc.
>
>
> Hi
> There's really *nothing* fancy here.
> Imagine a system with a microprocessor (with integrated cache), DDR and
> a PCI bus...
>
> Nicolas

Does it mean that you can interface both a DMA Engine along with
another logic(say some other FIFO, etc.) that use the memory on a same
DDR SDRAM Interface?... kinda think of that...