verilog versus vhdl

Hi Group

I have to implement a design which requires an FPGA, but to do so
among other things I obviousely first have to learn one of the two
mentioned languages. I got the impression that europe seems to be more
vhdl centric whereas verilog seems to be more popular in the US but
this argument alone is for reasons beond the scope of this question
not so important to me. I have a strong background in C programming
(should that matter anyhow) and in general experience with embedded
systems, but FPGAs are new to me. I'm otherwise completely open and
alas wonder what you guys suggest I should choose. I'm mostly
interested in replies from people which know both languages cause
otherwise I fear that this thread ends up in some sort of religious
war...

TIA

Markus

Markus Zingg wrote:
> Hi Group
> 
> I have to implement a design which requires an FPGA, but to do so
> among other things I obviousely first have to learn one of the two
> mentioned languages. I got the impression that europe seems to be more
> vhdl centric whereas verilog seems to be more popular in the US but
> this argument alone is for reasons beond the scope of this question
> not so important to me. I have a strong background in C programming
> (should that matter anyhow) and in general experience with embedded
> systems, but FPGAs are new to me. I'm otherwise completely open and
> alas wonder what you guys suggest I should choose. I'm mostly
> interested in replies from people which know both languages cause
> otherwise I fear that this thread ends up in some sort of religious
> war...
> 
> TIA
> 
> Markus
> 
Do not fear:  It'll end up in a religious war no matter what.

FWIW I'm a trained analog circuits & systems guy who usually adds value 
by architecting systems, designing control and communications 
algorithms, or implementing said algorithms in C or C++.  For years my 
job title was "software engineer" and the only circuit design I did was 
at home.

When I picked up FPGA design it was using Verilog because the two people 
I had to lean on for help were Verilog people.  I found it very easy and 
obvious, as long as I remembered that I was writing hardware 
descriptions, not writing "code".

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

"Applied Control Theory for Embedded Systems" came out in April.
See details at http://www.wescottdesign.com/actfes/actfes.html

Markus Zingg <m.zingg@nct.ch> wrote:

>Hi Group
>
>I have to implement a design which requires an FPGA, but to do so
>among other things I obviousely first have to learn one of the two
>mentioned languages. I got the impression that europe seems to be more
>vhdl centric whereas verilog seems to be more popular in the US but
>this argument alone is for reasons beond the scope of this question
>not so important to me. I have a strong background in C programming
>(should that matter anyhow) and in general experience with embedded
>systems, but FPGAs are new to me. I'm otherwise completely open and
>alas wonder what you guys suggest I should choose. I'm mostly
>interested in replies from people which know both languages cause
>otherwise I fear that this thread ends up in some sort of religious
>war...

I have a feeling VHDL is slightly more used than Verilog. You should
pick a language that you feel comfortable with. I never quite got the
grasp of Verilog (to me it seems like a description of a circuit
diagram instead of a structured language) so I choose to use VHDL.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Markus Zingg wrote:
> Hi Group
> 
> I have to implement a design which requires an FPGA, but to do so
> among other things I obviousely first have to learn one of the two
> mentioned languages. I got the impression that europe seems to be more
> vhdl centric whereas verilog seems to be more popular in the US but
> this argument alone is for reasons beond the scope of this question
> not so important to me. I have a strong background in C programming
> (should that matter anyhow) and in general experience with embedded
> systems, but FPGAs are new to me. I'm otherwise completely open and
> alas wonder what you guys suggest I should choose. I'm mostly
> interested in replies from people which know both languages cause
> otherwise I fear that this thread ends up in some sort of religious
> war...
> 
It certainly is a religious war :-)
FWIW, VHDL derives more from Ada, while Verilog derives from C.
This means that VHDL is strongly typed, while (classic) Verilog is not. 
That may be a plus or a minus, according to your viewpoint.

David R Brooks wrote:
> 
> It certainly is a religious war :-)

Yes.

> FWIW, VHDL derives more from Ada, while Verilog derives from C.

Yes.

> This means that VHDL is strongly typed, while (classic) Verilog is not.

Funnily enough, I did FPGA design using scehmatic entry during 
the  1990s with a little bit of VHDL (which I hated). I then 
became a software engineer for a number of years. Currently my 
favourite language is Ocaml which is at least as strongly typed
as ADA.

However, when I came back to FPGA design recently I gave Verilog 
a look and found that I much prefered it over VHDL. I prefer 
Verilog mostly because for me, I find it easier to map my ideas 
to the language. However, for FPGA design, I do think in logic 
rather than language.

Given the above, I'm sure it would be possible to find someone 
who says something similar to the above but swaps VHDL for 
Verilog.


Erik
-- 
+-----------------------------------------------------------+
  Erik de Castro Lopo
+-----------------------------------------------------------+
Open Source and Free Software means that you never sacrifice quality
of the code for meeting deadlines set up by people not participating
directly in the software development process.

Erik de Castro Lopo wrote:
> Given the above, I'm sure it would be possible to find someone
> who says something similar to the above but swaps VHDL for
> Verilog.

Or who can make a strong argument for C synthesis in certain markets.
System C, Streams-C (Impluse), Handel-C (Celoxica), or even FpgaC as it
matures this next year. As I work on new algorithms and technology
mapping for FpgaC I find myself amazed some days that the demo code is
natural coding in C, and better than difficult hand coding in
VHDL/Verilog in suprising cases. The original synthesis I got from TMCC
is both amazing sometimes, and sucks horribly others, but that
horribleness is going away soon with Beta-3 and Beta-4 releases the
second half of this year.

Both Handel-C and Streams C have their shining moments too, with their
commercial releases maturing into world class sythesis tools as well.
I've seen some pretty awesome projects implemented using Celoxica
tools.

John

fpga_toys@yahoo.com wrote:
> Erik de Castro Lopo wrote:
> > Given the above, I'm sure it would be possible to find someone
> > who says something similar to the above but swaps VHDL for
> > Verilog.
>
> Or who can make a strong argument for C synthesis in certain markets.
> System C, Streams-C (Impluse), Handel-C (Celoxica), or even FpgaC as it
> matures this next year. As I work on new algorithms and technology
> mapping for FpgaC I find myself amazed some days that the demo code is
> natural coding in C, and better than difficult hand coding in
> VHDL/Verilog in suprising cases. The original synthesis I got from TMCC
> is both amazing sometimes, and sucks horribly others, but that
> horribleness is going away soon with Beta-3 and Beta-4 releases the
> second half of this year.
>
> Both Handel-C and Streams C have their shining moments too, with their
> commercial releases maturing into world class sythesis tools as well.
> I've seen some pretty awesome projects implemented using Celoxica
> tools.
>
> John

I personally feel more comfortable with Verilog, but there are times
VHDL does a better job, and I use both (sometimes within one design).
I'm a hardware designer with a strong background in C (and a fair
amount of C++), so verilog feels more natural to me.

FWIW, my experience is that those who trained in hardware _tend_ to
prefer verilog, those who started more with strongly typed code _tend_
to prefer VHDL.

Cheers

PeteS

fpga_toys@yahoo.com wrote:

>
>Erik de Castro Lopo wrote:
>> Given the above, I'm sure it would be possible to find someone
>> who says something similar to the above but swaps VHDL for
>> Verilog.
>
>Or who can make a strong argument for C synthesis in certain markets.
>System C, Streams-C (Impluse), Handel-C (Celoxica), or even FpgaC as it
>matures this next year. As I work on new algorithms and technology
>mapping for FpgaC I find myself amazed some days that the demo code is
>natural coding in C, and better than difficult hand coding in
>VHDL/Verilog in suprising cases. The original synthesis I got from TMCC
>is both amazing sometimes, and sucks horribly others, but that
>horribleness is going away soon with Beta-3 and Beta-4 releases the
>second half of this year.

Sounds interesting. Got any websites?
BTW, when I studied electronics (about 10 years ago), I had to use a C
derivative based on the Gnu C compiler to create test patterns for a
piece of IC design.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Markus Zingg wrote:

> I have to implement a design which requires an FPGA, but to do so among
> other things I obviousely first have to learn one of the two mentioned
> languages. I got the impression that europe seems to be more vhdl
> centric whereas verilog seems to be more popular in the US but this
> argument alone is for reasons beond the scope of this question not so
> important to me. I have a strong background in C programming (should
> that matter anyhow) and in general experience with embedded systems, but
> FPGAs are new to me. I'm otherwise completely open and alas wonder what
> you guys suggest I should choose. I'm mostly interested in replies from
> people which know both languages cause otherwise I fear that this thread
> ends up in some sort of religious war...

There are industries and locations where your choice should be made by
looking at what others do.  Regardless which language is "best", picking
the language that few use locally or in the industry isn't wise.  This is
true both as an engineer, and as an employer.  Start by finding what the
local standard is, pick that, and move on. While nationwide there are more
openings for FPGA VHDL designers (Today on Monster.com, "verilog and fpga"
149 openings, "vhdl and fpga" 228 openings), there are clearly some
industries, types of applications, some companies and some geographic
areas that are very much the reverse. Try the same two searches for your
zip code, and/or for your industry, your application, your company.


-- 
Phil Hays (Xilinx, but writing for myself)

Markus Zingg wrote:
> Hi Group
>
> I have to implement a design which requires an FPGA, but to do so
> among other things I obviousely first have to learn one of the two
> mentioned languages. I got the impression that europe seems to be more
> vhdl centric whereas verilog seems to be more popular in the US but
> this argument alone is for reasons beond the scope of this question
> not so important to me. I have a strong background in C programming
> (should that matter anyhow) and in general experience with embedded
> systems, but FPGAs are new to me. I'm otherwise completely open and
> alas wonder what you guys suggest I should choose. I'm mostly
> interested in replies from people which know both languages cause
> otherwise I fear that this thread ends up in some sort of religious
> war...
>
> TIA
>
> Markus

google for verilog vhdl language wars, and google back in this group
for lots of previous points

Both languages have been under the auspices of one organisation for
some time now.

http://www.accellera.org/home

Verilog was in the past and still is much better at very low level
things typically done in ASICs such as working with ASIC std cell
libraries where VHDL models came much later. The EDA industry used to
favor it but after synthesis came along, translating both into a common
neutral format makes the point moot, you end up with the same thing.
ModelSim and other simulators have had a common internal format for
along time now.

VHDL was in the past and still is better at systems sorts of things and
appears to have more presence in FPGAs, military, edu, europe, telcos?
etc. I think though that ASIC design atleast in the US and Asia is
still mostly Verilog but there are exceptions to all the above.

Both languages overlap a lot, in pretty much the areas where most users
now work. verilog has recently been borrowing ideas from VHDL and is
generally a terser language.

You can easily compare their styles by checking out the big blue book
by Douglas J Smith in HDL Chip Design. The newer editions I believe
cover FPGAs too. Hives example suorces in both, along with nice
schematics and docs.

Myself I vote for the one that begins with V.

Now if the C language would pick up some major extensions the likes of
which we see in HDLs such as open ended bit sizes and the same notion
of concurrency and nested modules I could probably do most everthing in
a HDL C combined with regular C. If the compiler would spit out HDL for
regular synthesis and allow HDL code to be simulated at C speeds, that
would be neat.

John Jakson