100 Mbit manchester coded signal in FPGA

Hi all,

we are trying to implement a 100 MBit communication link witch uses
manchester coding. The signal is generated by a CPLD (xc2c64a) and we
hope we can receive it with an FPGA (Virtex4 for example).
Because the CPLD design will work at 2.5V and should use minimal power
(sensor node) my question is if it is possible to use a crystal with a
NOT-gate in the CPLD for generating the oszillator frequency instead
of an external oszillator.
The second question concerns the reception of the datastream within
the FPGA. My thought was to use a digital pll as mentioned here
http://www.erg.abdn.ac.uk/users/gorry/course/phy-pages/dpll.html
to generate a sample clock for the incomming bitstream.
With the help of a DCM module I would generate two 300 MHz clocks, one
shifted by 180 degree. Then I should be able to sample the incomming
stream with 600 MHz and I hope this is enough to stay phase locked
with the datastream. But I haven't done such a fast communication
before, so I've no idea if this will work. Any comments from you would
be nice.

Thanks,
 Michael

Michael,

The use of a CPLD or FPGA inversion is not recommended for a crystal
oscillator.

The problem is not that it won't work (it often does), it is that it
sometimes will not start.  The inversion also comes with a delay that is
not something that you can easily model and prove that the oscillator
will always start up.

Once started, it will oscillate, it is the starting that is sometimes
difficult,

Austin

Michael Dreschmann wrote:
> Hi all,
> 
> we are trying to implement a 100 MBit communication link witch uses
> manchester coding. The signal is generated by a CPLD (xc2c64a) and we
> hope we can receive it with an FPGA (Virtex4 for example).
> Because the CPLD design will work at 2.5V and should use minimal power
> (sensor node) my question is if it is possible to use a crystal with a
> NOT-gate in the CPLD for generating the oszillator frequency instead
> of an external oszillator.
> The second question concerns the reception of the datastream within
> the FPGA. My thought was to use a digital pll as mentioned here
> http://www.erg.abdn.ac.uk/users/gorry/course/phy-pages/dpll.html
> to generate a sample clock for the incomming bitstream.
> With the help of a DCM module I would generate two 300 MHz clocks, one
> shifted by 180 degree. Then I should be able to sample the incomming
> stream with 600 MHz and I hope this is enough to stay phase locked
> with the datastream. But I haven't done such a fast communication
> before, so I've no idea if this will work. Any comments from you would
> be nice.
> 
> Thanks,
>  Michael

Michael,
Comments inline.
"Michael Dreschmann" <michaeldre@gmx.de> wrote in message 
news:44d8c7e4.91526812@news.rhein-zeitung.de...
> Hi all,
>
> we are trying to implement a 100 MBit communication link witch uses
> manchester coding. The signal is generated by a CPLD (xc2c64a) and we
> hope we can receive it with an FPGA (Virtex4 for example).
> Because the CPLD design will work at 2.5V and should use minimal power
> (sensor node) my question is if it is possible to use a crystal with a
> NOT-gate in the CPLD for generating the oszillator frequency instead
> of an external oszillator.
No, I don't think this will work. You need an unbuffered inverter, don't 
think the CPLD will have this.
> The second question concerns the reception of the datastream within
> the FPGA. My thought was to use a digital pll as mentioned here
> http://www.erg.abdn.ac.uk/users/gorry/course/phy-pages/dpll.html
> to generate a sample clock for the incomming bitstream.
> With the help of a DCM module I would generate two 300 MHz clocks, one
> shifted by 180 degree. Then I should be able to sample the incomming
> stream with 600 MHz and I hope this is enough to stay phase locked
> with the datastream. But I haven't done such a fast communication
> before, so I've no idea if this will work. Any comments from you would
> be nice.
>
Yep, that works. I've recovered RZ data with a 4 times clock, same thing 
applies to Manchester coding, so you'd be able to do it with a 200MHz clock 
on the DDR IOB input registers. Check out XAPP224.
HTH, Syms. 

Michael Dreschmann schrieb:

> Hi all,
>
> we are trying to implement a 100 MBit communication link witch uses
> manchester coding. The signal is generated by a CPLD (xc2c64a) and we
> hope we can receive it with an FPGA (Virtex4 for example).
> Because the CPLD design will work at 2.5V and should use minimal power
> (sensor node) my question is if it is possible to use a crystal with a
> NOT-gate in the CPLD for generating the oszillator frequency instead
> of an external oszillator.
> The second question concerns the reception of the datastream within
> the FPGA. My thought was to use a digital pll as mentioned here
> http://www.erg.abdn.ac.uk/users/gorry/course/phy-pages/dpll.html
> to generate a sample clock for the incomming bitstream.
> With the help of a DCM module I would generate two 300 MHz clocks, one
> shifted by 180 degree. Then I should be able to sample the incomming
> stream with 600 MHz and I hope this is enough to stay phase locked
> with the datastream. But I haven't done such a fast communication
> before, so I've no idea if this will work. Any comments from you would
> be nice.
>
> Thanks,
>  Michael

you can look at the USB DPLL get the sub phy from opencores as example
it uses 4x clock to deliver mid-bit clock enable to latch the data.
something
similar should work for manchester as well.

cpld oscillator shure work, but you still need a resistor across not
gate in-out
it want oscillate otherwise. I have spent some time trying to get an
crystal
to swing on FPGA pins without external resistor but have not yet
succeeded.

Antti

"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag 
news:44D8D028.7080802@xilinx.com...
> Michael,
>
> The use of a CPLD or FPGA inversion is not recommended for a crystal
> oscillator.
>
> The problem is not that it won't work (it often does), it is that it
> sometimes will not start.  The inversion also comes with a delay that is
> not something that you can easily model and prove that the oscillator
> will always start up.
>
> Once started, it will oscillate, it is the starting that is sometimes
> difficult,
>
> Austin

hm you mean that an CPLD/FPGA NOT gate with 1 (or 2 resistors) and 2 caps 
and crystal will not oscillate under some conditions?

It should be 100% a-stable as it can not stay in non-oscillating state.

Antti 

Well, it might actually work, perhaps even reliably.
But I prefer a dedicated oscillator, because it uses less power, and
uses an internal chip that is optimized for the purpose, and is
manufactured by a company with expertise and a single-minded goal. And
it hardly costs extra...
Peter Alfke, Xilinx (back from vacation in Provence...:-)

Antti Lukats wrote:
> "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag
> news:44D8D028.7080802@xilinx.com...
> > Michael,
> >
> > The use of a CPLD or FPGA inversion is not recommended for a crystal
> > oscillator.
> >
> > The problem is not that it won't work (it often does), it is that it
> > sometimes will not start.  The inversion also comes with a delay that is
> > not something that you can easily model and prove that the oscillator
> > will always start up.
> >
> > Once started, it will oscillate, it is the starting that is sometimes
> > difficult,
> >
> > Austin
>
> hm you mean that an CPLD/FPGA NOT gate with 1 (or 2 resistors) and 2 caps
> and crystal will not oscillate under some conditions?
>
> It should be 100% a-stable as it can not stay in non-oscillating state.
> 
> Antti

On 8 Aug 2006 11:30:03 -0700, "Peter Alfke" <peter@xilinx.com> wrote:

>But I prefer a dedicated oscillator, because it uses less power, and
>uses an internal chip that is optimized for the purpose, and is
>manufactured by a company with expertise and a single-minded goal. And
>it hardly costs extra...

Costs are no problem, it's a university project and not a design for
production.
I thought a crystal in combination with the cpld would need less power
than a dedicated oscillator. Could you give me a hint where to find a
100 MHz low power oscialltor working at 2.5V? An external oscillator
of course would be easier.
An other question concerning power:
If I have a design that fits exactly in a xc2c64a cpld and I use the
next bigger one (xc2c128) with the same design how much more would be
the power consumption (roughly)?

Thanks,
 Michael

Antti,

That is exactly what I meant (and also echoed by other posters).

When is a not gate not a not?  When it has too much delay.

Austin



Antti Lukats wrote:
> "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag 
> news:44D8D028.7080802@xilinx.com...
>> Michael,
>>
>> The use of a CPLD or FPGA inversion is not recommended for a crystal
>> oscillator.
>>
>> The problem is not that it won't work (it often does), it is that it
>> sometimes will not start.  The inversion also comes with a delay that is
>> not something that you can easily model and prove that the oscillator
>> will always start up.
>>
>> Once started, it will oscillate, it is the starting that is sometimes
>> difficult,
>>
>> Austin
> 
> hm you mean that an CPLD/FPGA NOT gate with 1 (or 2 resistors) and 2 caps 
> and crystal will not oscillate under some conditions?
> 
> It should be 100% a-stable as it can not stay in non-oscillating state.
> 
> Antti 
> 
> 

Michael, I thought you wanted to use an FPGA (Virtex-4) for the
receiver.
Then you can use any oscillator frequency you want, and modify it with
the DCM inside the FPGA. The decoder design that I sent you has a very
wide data capture range, but slightly less when you go to 4x
oversampling (instead of my 8x).
Peter
==========
Michael Dreschmann wrote:
> On 8 Aug 2006 11:30:03 -0700, "Peter Alfke" <peter@xilinx.com> wrote:
>
> >But I prefer a dedicated oscillator, because it uses less power, and
> >uses an internal chip that is optimized for the purpose, and is
> >manufactured by a company with expertise and a single-minded goal. And
> >it hardly costs extra...
>
> Costs are no problem, it's a university project and not a design for
> production.
> I thought a crystal in combination with the cpld would need less power
> than a dedicated oscillator. Could you give me a hint where to find a
> 100 MHz low power oscialltor working at 2.5V? An external oscillator
> of course would be easier.
> An other question concerning power:
> If I have a design that fits exactly in a xc2c64a cpld and I use the
> next bigger one (xc2c128) with the same design how much more would be
> the power consumption (roughly)?
> 
> Thanks,
>  Michael

On 8 Aug 2006 13:52:43 -0700, "Peter Alfke" <peter@xilinx.com> wrote:

>Michael, I thought you wanted to use an FPGA (Virtex-4) for the
>receiver.
>Then you can use any oscillator frequency you want, and modify it with
>the DCM inside the FPGA.

Of course, I'm looking for an oscillator for the transmitting cpld. He
also needs 100 MHz to generate the data stream but as far as I know
there is now DCM or PLL in a CoolRunner 2. Or am I wrong?
On the receiver side power and oscillator is no problem.

Michael