Hi @ all, how can I simulate a testbench written in VHDL in QuartusII 3.0 software? Do I have to save it as a .vhd file or what kind of file is needed to simulate with Altera-Modelsim? Under SETTINGS --> EDA TOOL SETTINGS --> SIMULATION I choose ModelSim-Altera Under SETTINGS --> EDA TOOL SETTINGS ---> SIMULATION --> ADVANCED there can be chosen "Test Bench Mode". But when I want to select the Test Bench File there are only .vht files? How can I save a .vhd file as a .vht file? Thank you very much Kind regards A.Lapa
VHDL-Testbench-Simulation in QuartusII
Started by ●December 5, 2003
Reply by ●December 5, 20032003-12-05
ALuPin wrote:> how can I simulate a testbench written in VHDL in QuartusII 3.0 > software?Use modelsim. related thread: http://groups.google.com/groups?q=ranjith+oe_demo -- Mike Treseler
Reply by ●December 5, 20032003-12-05
http://www.altera.com/support/software/nativelink/quartus2/glossary/def_vht. html - Subroto Datta Altera Corp. A VHDL Test Bench File is the same as a standard VHDL test bench file, saved with a .vht extension. "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0312050619.24a357e6@posting.google.com...> Hi @ all, > > how can I simulate a testbench written in VHDL in QuartusII 3.0 > software? > > Do I have to save it as a .vhd file or what kind of file is needed > to simulate with Altera-Modelsim? > > Under SETTINGS --> EDA TOOL SETTINGS --> SIMULATION I choose > ModelSim-Altera > Under SETTINGS --> EDA TOOL SETTINGS ---> SIMULATION > --> ADVANCED > there can be chosen "Test Bench Mode". But when I want to select > the Test Bench File there are only .vht files? > How can I save a .vhd file as a .vht file? > > Thank you very much > > Kind regards > A.Lapa
Reply by ●December 8, 20032003-12-08
"Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>...> http://www.altera.com/support/software/nativelink/quartus2/glossary/def_vht. > html > > - Subroto Datta > Altera Corp. > > > > > A VHDL Test Bench File is the same as a standard VHDL test bench file, saved > with a .vht extension. >Hi, yes I read about it in the handbook, but HOW can I save a .vhd file as a .vht file? When I write a testbench file I can only save it as .vhd ! ? Thank you.
Reply by ●December 8, 20032003-12-08
In this case rename your vhd file which contains the testbench to the .vht extension using the Windows Explorer or DOS prompt. - Subroto "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0312072313.3cd8ecc@posting.google.com...> "Subroto Datta" <sdatta@altera.com> wrote in messagenews:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>...> >http://www.altera.com/support/software/nativelink/quartus2/glossary/def_vht.> > html > > > > - Subroto Datta > > Altera Corp. > > > > > > > > > > A VHDL Test Bench File is the same as a standard VHDL test bench file,saved> > with a .vht extension. > > > > > Hi, > > yes I read about it in the handbook, but HOW can I save a .vhd file as > a .vht file? > > When I write a testbench file I can only save it as .vhd ! ? > > Thank you.
Reply by ●December 15, 20032003-12-15
> In this case rename your vhd file which contains the testbench to the .vht > extension using the Windows Explorer or DOS prompt. > > - SubrotoHi, are the following settings right ? Settings --> EDA Tool Settings --> Advanced VHDL Simulation Options --> Test Bench Mode: Test Bench File: ...tb_reservoir_positions.vht Test Bench entity name: ...tb_reservoir_positions.vht reservoir_positions.vhd is the module to be simulated (and therefore it is instantiated in the testbench tb_reservoir_positions.vht) There seems to be some problem with it because after compiling I get the following error messages: - Error: Compilation of design file Reservoir_positions.vho was NOT successful - ModelSim couldn't execute "vcom": no such file or directory - Error: Compilation of test bench file ... tb_reservoir_positions.vht was NOT successful - Error: Simulation of design tb_reservoir_positions.vht was NOT successful Thanks Andre V.
Reply by ●December 15, 20032003-12-15
"Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>...> > A VHDL Test Bench File is the same as a standard VHDL test bench file, saved > with a .vht extension. >Why do vendors insist on using non-standard extensions for VHDL (and Verilog) source files? (Altera's not the only one.) Emacs, for example, knows that a .vhd file is VHDL and a .v file is Verilog. It doesn't know about a .vht file, unless I go and tell it. ModelSim recognizes .vhd and .v files but doesn't know from .vht files. The solution, of course, is to rename the files created by the tools. FWIW, I've adopted a simple notation to indicate that a file is a test bench: given a module foo.vhd, its test bench is called foo_tb.vhd. --a
Reply by ●December 15, 20032003-12-15
ALuPin wrote:> - ModelSim couldn't execute "vcom": no such file or directory > - Error: Compilation of test bench file ... tb_reservoir_positions.vht was NOT > successful > - Error: Simulation of design tb_reservoir_positions.vht was NOT successfulConsider vcom and vsim from the command line, not from Quartus. -- Mike Treseler
Reply by ●December 16, 20032003-12-16
> Consider vcom and vsim from the command line, not from Quartus. > > -- Mike TreselerHi Mike, ok let's consider vcom and vsim from the command line ... what does I learn from it? :o) Thanks. Kind regards Andre V.
Reply by ●December 16, 20032003-12-16
Bassman59a@yahoo.com (Andy Peters) writes:> "Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>... > > > > > A VHDL Test Bench File is the same as a standard VHDL test bench file, saved > > with a .vht extension. > > > > Why do vendors insist on using non-standard extensions for VHDL (and > Verilog) source files? (Altera's not the only one.) > > Emacs, for example, knows that a .vhd file is VHDL and a .v file is > Verilog. It doesn't know about a .vht file, unless I go and tell it. > ModelSim recognizes .vhd and .v files but doesn't know from .vht > files. > > The solution, of course, is to rename the files created by the tools. >For emacs , the solution is to stick this sort of thing in your .emacs file: (setq auto-mode-alist (append '(("\\.vht?$" . vhdl-mode)) auto-mode-alist)) Tweak the "vht" to suit... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
