synthesis intelligence of quartus regarding range of values

I got a "circuit", which is doing integer division with large values. I
instantiated a MEGAWIZ-devider with currently 48bits / 16 Bits, which
ist fed with some more bits (done be shifting) in order to obtain a
result with a higher accuracy than 1 in one step without proceeding the
remainder.

E.g. I am shifting with 10 Bits and fill the rest with zero:
input <= "0000" & Value (33 downto 0) & "0000000000"

I recognize, that Quartus is obviously capable of synthesizing away to
signals / paths in the devider which are not needed.

Now, what is about the range of values ? In my design, the A / B have a
certain relationship, so that the result can never exceed 18 bits,
whereby the vector of the result (devider out) has of course 48 bits.

Is it of an advantage if the range of values is restricted?

Currently I am cutting away the first bits, which will always be zero.
s there anything more, I can do, to keep the design small ?

No Idea about that?

Another example:

Assuming two counters from 0 to 10000 are multiplied. The result will
be only 27 bits long, where the vectors (at least 14 bits each) would
lead to one bit more ?

homoalteraiensis wrote:

> Assuming two counters from 0 to 10000 are multiplied. The result will
> be only 27 bits long, where the vectors (at least 14 bits each) would
> lead to one bit more ?

I would write some hdl code and run a simulation
to answer questions like that.

          -- Mike Treseler

?

A multiplier with two 14 bit ports (as 10,000 = 0x2710H or 14 bits),
e.g. the resulting operation has two 14 bit inputs, but some simple math
(as in multiply 10,000 by 10,000) shows that the result requires only 27
bits (0x5F5E100H) as the input range is restricted.

So, the MSB of the multiplier would never be asserted (used), and if
this was a multiplier that was being synthesized, perhaps the tools are
very smart, and because of the restricted range of the input variables,
the output is recognized as not needing all 28 bits, and the unused
logic is not created to begin with?

That is awfully smart for the tools, as how did they "know" that the 14
bit inputs did not go to 0x3FFFH? (Who told the tools?)  Is there a
"range" menu for the multiplier function generator?

Austin

Try looking at this from the POV of the output, rather than the
inputs...

If you only hook up the lower 27 bits of the output, then the synthesis
tool will know that the upper bit is never used (not the same as "never
is one"), and optimize it out, to the extent possible in the hardware.

In VHDL,  you could use constrained integer types, that would
automatically stop the simulation with an attempted assignment that is
out of the range of the target variable/signal.  This can be used on
non-power-of-two limits also.

signal terma, termb : natural range 0 to 10000;
signal product : natural range 0 to 10000 * 10000;

Andy


Austin Lesea wrote:
> ?
>
> A multiplier with two 14 bit ports (as 10,000 = 0x2710H or 14 bits),
> e.g. the resulting operation has two 14 bit inputs, but some simple math
> (as in multiply 10,000 by 10,000) shows that the result requires only 27
> bits (0x5F5E100H) as the input range is restricted.
>
> So, the MSB of the multiplier would never be asserted (used), and if
> this was a multiplier that was being synthesized, perhaps the tools are
> very smart, and because of the restricted range of the input variables,
> the output is recognized as not needing all 28 bits, and the unused
> logic is not created to begin with?
>
> That is awfully smart for the tools, as how did they "know" that the 14
> bit inputs did not go to 0x3FFFH? (Who told the tools?)  Is there a
> "range" menu for the multiplier function generator?
> 
> Austin

"homoalteraiensis" <fpgaengineerfrankfurt@arcor.de> wrote in message 
news:1155228893.682178.172540@p79g2000cwp.googlegroups.com...
>I got a "circuit", which is doing integer division with large values. I
> instantiated a MEGAWIZ-devider with currently 48bits / 16 Bits, which
> ist fed with some more bits (done be shifting) in order to obtain a
> result with a higher accuracy than 1 in one step without proceeding the
> remainder.
>
> E.g. I am shifting with 10 Bits and fill the rest with zero:
> input <= "0000" & Value (33 downto 0) & "0000000000"
>
> I recognize, that Quartus is obviously capable of synthesizing away to
> signals / paths in the devider which are not needed.
>
> Now, what is about the range of values ? In my design, the A / B have a
> certain relationship, so that the result can never exceed 18 bits,
> whereby the vector of the result (devider out) has of course 48 bits.
>
> Is it of an advantage if the range of values is restricted?
>
> Currently I am cutting away the first bits, which will always be zero.
> s there anything more, I can do, to keep the design small ?


If the result never exceeds 18 bits, I'd suggest writing the routine 
yourself.  If your device supports an add/subtract structure, you need 18 
stages to get 18 bits of result while the 48 stages produced with the 
MegaWizard might be more of a problem to optimize.

By having the dividend start off in the correct range relative to the 
divisor, you only need 34 bits divided by 18 bits to give you your 
consistent 18 bit result.  Any more bits just change add fractional bits to 
the remainder.

If you could specify whether either value is signed and what the dividend 
and divisor ranges are, I'd happily email you an excel spreadsheet showing 
how the equations come together for the add/sub stages.  Also please verify 
that you don't need the remainder. 

Ah ha,

I knew that somewhere the ranges had to be described.

Since I don't code in VHDL, I didn't know.

Thanks.  Mystery solved.

Austin

"John_H" <newsgroup@johnhandwork.com> wrote in message 
news:un1Eg.7568$oa1.3750@news02.roc.ny...
> By having the dividend start off in the correct range relative to the 
> divisor, you only need 34 bits divided by 18 bits to give you your 
> consistent 18 bit result.  Any more bits just change add fractional bits 
> to the remainder.

That should be "34 bits divided by 16 bits to give you your consistent 18 
bit result" 

Mike Treseler schrieb:

> I would write some hdl code and run a simulation
> to answer questions like that.
>

How can the Simulation "know", in which way the mathematical function
is realized, and if a synthesis tool can save particular resoures in a
certain FPGA type?

Anyway, I did some experiments with signal assignments and had a look
at the required resources in Quartus. As expected, the number of used
multiplier signals directly corresponds to the number of outputs
signals. But the number of MULs this is not so obvious to me. In one
case, I expected at least 8 9-bit-MULs to be used, where Quartus only
used 6. Hm...

homoalteraiensis wrote:

> How can the Simulation "know", in which way the mathematical function
> is realized, and if a synthesis tool can save particular resoures in a
> certain FPGA type?

Simulation lets me explore the logical description
and do the math. Integer ranges vs bit widths etc.
Synthesis finds a netlist to match the description.
Perhaps I misunderstood your question.

     -- Mike Treseler