NgdBuild:604 error

Hi,

I'm tearing my hair out and I can't find the answer to this in any of
the Xilinx solutions!!!

---8<------8<------8<------8<------8<------8<------8<------8<------8<---
NgdBuild:604 - logical block 'pace_inst/U_Game/vram_inst' with type
vram' could not be resolved. A pin name misspelling can cause this, a
missing edif or ngc file, or the misspelling of a type name. Symbol
'vram' is not supported in target 'spartan3'.
---8<------8<------8<------8<------8<------8<------8<------8<------8<---

'vram' was generated with coregen and is a block memory. I copied the
.NGC file to my project directory and associated it with the instance in
the source tree. The VHDL file in which it is instantiated has a
component entry for vram.

I also notice during synthesis I get...

WARNING:Xst:766 - line 453: Generating a Black Box for component <vram>.

What am I doing wrong??? What have I forgotten?

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:

> What am I doing wrong??? What have I forgotten?

I guess I should also add that I'm doing all this in the ISE 8.1i
Webpack Edition IDE, not the command-line.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

On Fri, 11 Aug 2006 17:25:59 +1000, Mark McDougall <markm@vl.com.au> wrote:

>Hi,
>
>I'm tearing my hair out and I can't find the answer to this in any of
>the Xilinx solutions!!!
>
>---8<------8<------8<------8<------8<------8<------8<------8<------8<---
>NgdBuild:604 - logical block 'pace_inst/U_Game/vram_inst' with type
>vram' could not be resolved. A pin name misspelling can cause this, a
>missing edif or ngc file, or the misspelling of a type name. Symbol
>'vram' is not supported in target 'spartan3'.
>---8<------8<------8<------8<------8<------8<------8<------8<------8<---
>
>'vram' was generated with coregen and is a block memory. I copied the
>.NGC file to my project directory and associated it with the instance in
>the source tree. The VHDL file in which it is instantiated has a
>component entry for vram.

I get this error if I do not import the vram.xco file into the project explicitely by hand.
Even though the core generator asks for the project and should know what is needed.
I think earlier versions than ISE 8.1.? worked without that, but I'm not sure. 
(I use virtex4, Ise8.1.current_sp)
>
>I also notice during synthesis I get...
>
>WARNING:Xst:766 - line 453: Generating a Black Box for component <vram>.

You can declare the black box yourself, then you get only 1999 warnings
instead of 2000.

What annoys me more is self critic like "You use dirty and unsave coding tricks
like clock gating" that comes from inside the MicroBlaze    and endless lists
of unconnected and removed signals from inside of automatically generated 
FIR-filters or multipliers.

Why can't ISE respect it when I explicitely write

....
           carry_out  => open,
....

It's not that I forgot to connect the pin.
Now use name mangling like

	carry_out => carry_out_unused678,

and leave that unconnected. Then the false alarm is obvious at first glance.


regards, Gerhard

Mark McDougall wrote:
> Hi,
>
> I'm tearing my hair out and I can't find the answer to this in any of
> the Xilinx solutions!!!
>
> ---8<------8<------8<------8<------8<------8<------8<------8<------8<---
> NgdBuild:604 - logical block 'pace_inst/U_Game/vram_inst' with type
> vram' could not be resolved. A pin name misspelling can cause this, a
> missing edif or ngc file, or the misspelling of a type name. Symbol
> 'vram' is not supported in target 'spartan3'.
> ---8<------8<------8<------8<------8<------8<------8<------8<------8<---
>
it seems like that NgdBuild just can not find the netlist file for the
vram. Not quite sure why. 

Felix

Gerhard Hoffmann wrote:

> I get this error if I do not import the vram.xco file into the
> project explicitely by hand. Even though the core generator asks for
> the project and should know what is needed. I think earlier versions
> than ISE 8.1.? worked without that, but I'm not sure. (I use virtex4,
> Ise8.1.current_sp)

Thanks! I discovered that using "Insert New Source" and generating the
core within the project did actually associate the .xco file with the
instance and I *finally* got the project to build, after much frustration.

However, during the process coregen asked me for a directory which it
subsequently ignored, instead placing everything in the project root
directory.

I used to swear at Quartus, but now I have a new-found appreciation for
it! And whoever decided that the ISE files should be binary... just give
me *two* minutes alone with them... >:/

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

On Mon, 14 Aug 2006 10:24:02 +1000, Mark McDougall <markm@vl.com.au> wrote:

>I used to swear at Quartus, but now I have a new-found appreciation for
>it! And whoever decided that the ISE files should be binary... just give
>me *two* minutes alone with them... >:/

But please, let me watch it  :-)

Gerhard

Gerhard Hoffmann wrote:

> But please, let me watch it  :-)

I hope you have a strong stomach! ;)

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall wrote:
[snip]
>
> I used to swear at Quartus, but now I have a new-found appreciation for
> it! And whoever decided that the ISE files should be binary... just give
> me *two* minutes alone with them... >:/
>

The new ISE versions with the binary project files can still read the
old .npl project file format and convert it to the new style.  This is
a very useful way to back up your project settings.  There is a
drawback, that the settings are now entered by hand (or using
ISE 6.1i or earlier) AND you must keep a backup of the .npl
file before allowing the newer ISE to convert it (the .npl file
gets trashed in the conversion process).  But having this file
around is very handy for the cases where ISE "blows up" and
leaves you with an unusable .ise project file.  Otherwise when
(notice I didn't say "if") your .ise project file becomes unusable
you need to start fresh.

Good Luck,
Gabor

Gabor wrote:

> Otherwise when
> (notice I didn't say "if") your .ise project file becomes unusable
> you need to start fresh.

I know I'm not the first to complain about having binary project files,
so I'm not sure why Xilinx won't *listen* and change it. Not only do you
have the above-mentioned problem, but it also means you can't track
changes using an external revision control system. And that's a pretty
serious problem!

At least with Quartus, the entire project configuration is captured in
two human-readable text files. And when you're working with multiple
configurations of the same project during development, it's a god-send
that you can simply diff the project files!

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

I get the same thing myself,

I'm having to add the xco file and re-generate. I'm using 8.1 sp 3.
Does anyone know if this is fixed in later versions, or have a better
idea what's causing the problem?

regards,
Robin

Gerhard Hoffmann wrote:
> On Fri, 11 Aug 2006 17:25:59 +1000, Mark McDougall <markm@vl.com.au> wrote:
>
> >Hi,
> >
> >I'm tearing my hair out and I can't find the answer to this in any of
> >the Xilinx solutions!!!
> >
> >---8<------8<------8<------8<------8<------8<------8<------8<------8<---
> >NgdBuild:604 - logical block 'pace_inst/U_Game/vram_inst' with type
> >vram' could not be resolved. A pin name misspelling can cause this, a
> >missing edif or ngc file, or the misspelling of a type name. Symbol
> >'vram' is not supported in target 'spartan3'.
> >---8<------8<------8<------8<------8<------8<------8<------8<------8<---
> >
> >'vram' was generated with coregen and is a block memory. I copied the
> >.NGC file to my project directory and associated it with the instance in
> >the source tree. The VHDL file in which it is instantiated has a
> >component entry for vram.
>
> I get this error if I do not import the vram.xco file into the project explicitely by hand.
> Even though the core generator asks for the project and should know what is needed.
> I think earlier versions than ISE 8.1.? worked without that, but I'm not sure.
> (I use virtex4, Ise8.1.current_sp)
> >
> >I also notice during synthesis I get...
> >
> >WARNING:Xst:766 - line 453: Generating a Black Box for component <vram>.
>
> You can declare the black box yourself, then you get only 1999 warnings
> instead of 2000.
>
> What annoys me more is self critic like "You use dirty and unsave coding tricks
> like clock gating" that comes from inside the MicroBlaze    and endless lists
> of unconnected and removed signals from inside of automatically generated
> FIR-filters or multipliers.
>
> Why can't ISE respect it when I explicitely write
>
> ....
>            carry_out  => open,
> ....
>
> It's not that I forgot to connect the pin.
> Now use name mangling like
>
> 	carry_out => carry_out_unused678,
>
> and leave that unconnected. Then the false alarm is obvious at first glance.
> 
> 
> regards, Gerhard