Embedded clocks

rickman wrote:
> Jim Granville wrote:
> 
>>rickman wrote:
>>
>>
>>>Jim Granville wrote:
>>>
>>>
>>>>anything better than RC, has starting time issues, so usually runs
>>>>all the time, and that has power penalties.
>>>
>>>
>>>RC is not even an oscillator without other componets so it really is
>>>not a solution.  I can get an oscillator that runs on 1 mA of current,
>>>costs under $0.50 and has plenty of accuracy to do any of the above
>>>protocols.  So async serial is ok.  One in and one out.
>>
>>RC osc would use the CPLD - not sure what 'other components' you mean.
>>
>>If you are happy with 1mA and 50c, then that's fine.
>>
>>I see in my notes, Core ICC figures of ~20uA @ 15KHz for a CPLD RC osc,
>>at a cost of a few cents. ( and appx 50uA at 1MHz )
> 
> 
> How do you get a CPLD to reliably oscillate with an RC?

Choose one with Schmitt pin options (also important if you want to try 
i2c, where the slow edges will mess with non-schmitt CPLDs ).

That's Atmel's ATF1502BE (32MC), or CoolrunnerII devices.

You can make 1 pin, 2 pin, or 3 pin Oscillators - the more pins,
the better the precision, and less it depends on the thresholds.

The numbers I gave are for ATF1502BE.

-jg

rickman wrote:
<snip>

> It just occured to me that I really don't need to know the format of
> the data if I just treat the signals as arbitrary data streams.  I can
> sample them at high enough rates that the timing information is not
> significantly distorted and send them across in a very, very simple
> scheme.  I can sample each one in a round-robin manner at say 1 MHz for
> a total clock rate of 10 MHz (10 signals in one direction, 2 in the
> other).  This interface would need a clock, datain, dataout and frame
> sync.  

If you use Sync related direction control ( see SPI memories ), you can
share/common the datain/dataout : eg the first 12 clocks are one way, 
the last 4 are the other way, in a simple 16 clock frame, with spare room )
-jg

rickman wrote:
>
> How do you get a CPLD to reliably oscillate with an RC?
>

If you can afford 2 more CPLD pins, Peter described it for an FPGA, but
should work for CPLD:

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy&iLanguageID=1&iCountryID=1

I'm curious:
1) how well does that circuit scale up in frequency,
2) what your frequency needs are?

As described, using 470K resistors, the power for that 3 pin RC
oscillator looks miniscule.
Add a little more gating, you can even shut it off, and re-start time
doesn't look much more than half a clock period.

JustJohn wrote:

> rickman wrote:
> 
>>How do you get a CPLD to reliably oscillate with an RC?
>>
> 
> 
> If you can afford 2 more CPLD pins, Peter described it for an FPGA, but
> should work for CPLD:
> 
> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy&iLanguageID=1&iCountryID=1
> 
> I'm curious:
> 1) how well does that circuit scale up in frequency,
> 2) what your frequency needs are?
> 
> As described, using 470K resistors, the power for that 3 pin RC
> oscillator looks miniscule.

RC Osc power is not just resistor power; a significant amount is the
linear-region Icc from the pin buffers that are not square wave driven.


> Add a little more gating, you can even shut it off, and re-start time
> doesn't look much more than half a clock period.

Restart time is instant, but you do need to watch the start(idle) values 
as the first half cycle time can differ from the others, as the circuit 
changes from rest state, to the ping-pong oscillation cycles.

With 3 terminal Osc's, you should also design the Pinout/PCB, so the
'linear' node is adajcent to the positive acting pin(cap), and not the 
negative acting pin. eg a good pinout is : GND RC Cap+ Res-

-jg

Jim Granville wrote:
> rickman wrote:
> > How do you get a CPLD to reliably oscillate with an RC?
>
> Choose one with Schmitt pin options (also important if you want to try
> i2c, where the slow edges will mess with non-schmitt CPLDs ).
>
> That's Atmel's ATF1502BE (32MC), or CoolrunnerII devices.
>
> You can make 1 pin, 2 pin, or 3 pin Oscillators - the more pins,
> the better the precision, and less it depends on the thresholds.
>
> The numbers I gave are for ATF1502BE.

The ATF15xx and Coolrunner II are no gos because of the dual voltages
required.  Also the ATF parts only come in the relatively huge TQFP44
packages which are four times larger than the csBGA of the Coolrunner
parts.  I can make a schmitt trigger easily enough with a couple of
resistors and an output pin.

How about some details on the RC oscillator?  I have not seen a 3 pin
oscillator before.

rickman wrote:

> Jim Granville wrote:
> 
>>rickman wrote:
>>
>>>How do you get a CPLD to reliably oscillate with an RC?
>>
>>Choose one with Schmitt pin options (also important if you want to try
>>i2c, where the slow edges will mess with non-schmitt CPLDs ).
>>
>>That's Atmel's ATF1502BE (32MC), or CoolrunnerII devices.
>>
>>You can make 1 pin, 2 pin, or 3 pin Oscillators - the more pins,
>>the better the precision, and less it depends on the thresholds.
>>
>>The numbers I gave are for ATF1502BE.
> 
> 
> The ATF15xx and Coolrunner II are no gos because of the dual voltages
> required. 

  What we need is a CPLD like the Freescale RS08, or the SiLabs 
C8051F41x - that works from 1.8V to 5.5V, and draws 1uA static Icc :)
  [ ATF1502BE draws 2.3uA, but needs two rails.... ]


> Also the ATF parts only come in the relatively huge TQFP44
> packages which are four times larger than the csBGA of the Coolrunner
> parts.  

  Yes, I have already mentioned to Atmel that TQFP44 is large in today's 
designs....

> I can make a schmitt trigger easily enough with a couple of
> resistors and an output pin.
> 
> How about some details on the RC oscillator?  I have not seen a 3 pin
> oscillator before.

One Pin : Bidirectional pin, Open Collector, Res Pullup, Swings between 
Schmitt VthP and VthN - Tolerance is that of Hyst Band.
Duty cycle is narrow. Hard to gate, as CAP is never 0V.
Can VCO modulate.

Two Pin A : Bidirectional pins ( see 4046 ) Open Collector, Res Pullups,
Swings from GND to VthP, Nominally 50% duty cycle. Gates very well
Can VCO modulate.


Two Pin B : One IP, one OP, Classic HC14 Osc, single Rfb, and Cap, 
Swings VthP to VthN, Duty cycle is nominally 50%, Poor VCO modulation.

Three Pin: One IP and 2 OPs. (See 4060, 4541 et al) Positive feedback to 
a CAP, negative feedback via resistor, with optional overshoot resistor 
from CAP to IP pin. Needs layout to have +ve FB next to RC IP pin.
Has nominal immunity to pin thresholds, and some PSRR, poor VCO modulation.

Gives lowest Icc, as the signal spends least time in high current IP 
regions.

Simplest form, is a non-inverter, followed by inverter (order matters).


Can have latches added, to 'de-fur' and can be gated with a little care.

See the other link in this thread
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy&iLanguageID=1&iCountryID=1

This is a 3 termal RC osc, with a SR latch.

-jg

Jim Granville wrote:
> JustJohn wrote:
> > As described, using 470K resistors, the power for that 3 pin RC
> > oscillator looks miniscule.
>
> RC Osc power is not just resistor power; a significant amount is the
> linear-region Icc from the pin buffers that are not square wave driven.
>
1) (Jim) Do you have a more precise quantifier than "significant"?

To be clear, I'll be referring to Peter's circuit (I can't post one
myself, and am too lazy right now to attempt ASCII artwork). Let's call
the top resistor Rc, since it charges the Cap, and call the bottom one
Rs, since it feeds a Sense pin. This simple circuit brings a nice
collection of subtleties with it:..

There are roughly three regions of operation (six, it's a symmetric
circuit, let's look at just after switching C to ground):
A) Immediately after switching , C has pushed Rs to VCC/2 below ground,
and C is charging through both Rc (via the inverted output pin) and and
Rs (via the sense pin protection diode).
B) Some time later, the sense pin protection diode is no longer fwd
biased, and C is charging through Rc only. Rs serves only to connect C
to the sense pin (I'll assume that frequency is low enough that sense
pin capacitance can be ignored).
C) Sense pin reaches linear region, starts causing Icc current draw, in
addition to the charging current Rc.

 I hadn't thought much about FPGA input structure before this. I had
generally assumed, unlike logic buffers such as 'ALVC245 and the like,
whose totem-pole inputs can consume enough power near threshold to
destroy themselves, that newer multistandard FPGA inputs were more like
a comparator, and not subject to damage, or even very much increase in
current when near threshold. There are no warnings in the
datasheet...certainly no "Icc current vs. input voltage" chart to
indicate that near threshold operation is of concern..

2) Can anyone say anything about Icc vs. input level for either FPGAs
or, eg. CoolRunnrer PLDs?

> > Add a little more gating, you can even shut it off, and re-start time
> > doesn't look much more than half a clock period.
>
> Restart time is instant, but you do need to watch the start(idle) values
> as the first half cycle time can differ from the others, as the circuit
> changes from rest state, to the ping-pong oscillation cycles.

Of course charging starts immediately, I meant the time from enable to
the 1st threshold crossing at the sense pin. I was wrong in saying
"more" than half a clock period. The first half period should be
shorter than periods that follow, because C only has to charge from
ground to threshold, while in later half periods, C  charges from
~VCC/2 below ground to threshold.

> With 3 terminal Osc's, you should also design the Pinout/PCB, so the
> 'linear' node is adajcent to the positive acting pin(cap), and not the
> negative acting pin. eg a good pinout is : GND RC Cap+ Res-
>

JustJohn wrote:
> Jim Granville wrote:
> 
>>JustJohn wrote:
>>
>>>As described, using 470K resistors, the power for that 3 pin RC
>>>oscillator looks miniscule.
>>
>>RC Osc power is not just resistor power; a significant amount is the
>>linear-region Icc from the pin buffers that are not square wave driven.
>>
> 
> 1) (Jim) Do you have a more precise quantifier than "significant"?

For a good example graph, look at the data of the 74LVC14A, Fig 9 on my 
copy.

http://www.standardics.philips.com/products/lvc/pdf/74lvc14a.pdf

Here, you'll see the classic double peaks of a Schmitt transfer.
Non-Schmitts are worse: Similar skirts, but with a single, higher peak.

There can be variations in the peaks, and skirt shapes.

A two terminal Osc will trace the 'butterfly' between the peaks, and so 
average 4mA Icc on this device.
A three terminal osc is appx 25-30% of that.


> To be clear, I'll be referring to Peter's circuit (I can't post one
> myself, and am too lazy right now to attempt ASCII artwork). Let's call
> the top resistor Rc, since it charges the Cap, and call the bottom one
> Rs, since it feeds a Sense pin. This simple circuit brings a nice
> collection of subtleties with it:..
> 
> There are roughly three regions of operation (six, it's a symmetric
> circuit, let's look at just after switching C to ground):
> A) Immediately after switching , C has pushed Rs to VCC/2 below ground,
> and C is charging through both Rc (via the inverted output pin) and and
> Rs (via the sense pin protection diode).
> B) Some time later, the sense pin protection diode is no longer fwd
> biased, and C is charging through Rc only. Rs serves only to connect C
> to the sense pin (I'll assume that frequency is low enough that sense
> pin capacitance can be ignored).
> C) Sense pin reaches linear region, starts causing Icc current draw, in
> addition to the charging current Rc.
> 
>  I hadn't thought much about FPGA input structure before this. I had
> generally assumed, unlike logic buffers such as 'ALVC245 and the like,
> whose totem-pole inputs can consume enough power near threshold to
> destroy themselves, that newer multistandard FPGA inputs were more like
> a comparator, and not subject to damage, or even very much increase in
> current when near threshold. There are no warnings in the
> datasheet...certainly no "Icc current vs. input voltage" chart to
> indicate that near threshold operation is of concern..

I'm not sure about damage, but certainly the 4mA linear region of the
LVC14a example, might play havoc with someones uA power budget.

Modern FPGAs are pretty poor low power devices, so you'll likely just 
get a shrug from their vendors, but some CPLDs are sub 20uA, and so this 
can be important. It _should_ be in the uA CPLD data sheets.

I have to smile at the MAX II low power marketing spin, where they
REMOVE the power, to claim 'low power', and add many discrete components 
to do this. Remember Resistor-Transistor Logic ?

> 
> 2) Can anyone say anything about Icc vs. input level for either FPGAs
> or, eg. CoolRunnrer PLDs?

It is not hard to measure this, especially once you understand the basic 
shape, and the peak(s) you are looking for.
You do need to have a low voltage drop across the current sense.

-jg

"Brian Davis" <brimdavis@aol.com> wrote in message 
news:1155472497.883314.66650@m79g2000cwm.googlegroups.com...
>
> I haven't tried that out yet, but I don't see any fundamental problems
> with it ( other than wasting BW vs. other modulation schemes. )
>
> Brian
>
Hi Brian,
Neat. I guess a problem could be that the signal has some data dependent DC 
component. But 8B10B coding fixes that.
Cheers, Syms. 

Jim Granville wrote:
>   What we need is a CPLD like the Freescale RS08, or the SiLabs
> C8051F41x - that works from 1.8V to 5.5V, and draws 1uA static Icc :)
>   [ ATF1502BE draws 2.3uA, but needs two rails.... ]

The Coolrunner XPLA3 parts are pretty good.  Other than not having
schmitt trigger inputs, what don't you like about them?

> > How about some details on the RC oscillator?  I have not seen a 3 pin
> > oscillator before.
>
> One Pin : Bidirectional pin, Open Collector, Res Pullup, Swings between
> Schmitt VthP and VthN - Tolerance is that of Hyst Band.
> Duty cycle is narrow. Hard to gate, as CAP is never 0V.
> Can VCO modulate.

If I understand correctly, this circuit would generate a sawtooth on
the cap with a very short low drive time on the output.

> Two Pin A : Bidirectional pins ( see 4046 ) Open Collector, Res Pullups,
> Swings from GND to VthP, Nominally 50% duty cycle. Gates very well
> Can VCO modulate.

I don't get this one at all.  I looked up the 4046 but all descriptions
I could find treat the VCO as a black box.  I am guessing that the two
pins are driven with opposite polarity and the cap is grounded at one
end or the other all the time.  So it would be charged like the one pin
approach and then discharged like the one pin approach.  So this is a
pair of the one pin drivers to give you 50/50 duty cycle?

This seems simple.  Any issues with startup? Does it need FFs anywhere
to make it work without noise?  I would think that the lack of schmitt
trigger inputs would require a FF.


> Two Pin B : One IP, one OP, Classic HC14 Osc, single Rfb, and Cap,
> Swings VthP to VthN, Duty cycle is nominally 50%, Poor VCO modulation.

This one I know.


> Three Pin: One IP and 2 OPs. (See 4060, 4541 et al) Positive feedback to
> a CAP, negative feedback via resistor, with optional overshoot resistor
> from CAP to IP pin. Needs layout to have +ve FB next to RC IP pin.
> Has nominal immunity to pin thresholds, and some PSRR, poor VCO modulation.
>
> Gives lowest Icc, as the signal spends least time in high current IP
> regions.
>
> Simplest form, is a non-inverter, followed by inverter (order matters).
>
>
> Can have latches added, to 'de-fur' and can be gated with a little care.
>
> See the other link in this thread
> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy&iLanguageID=1&iCountryID=1
>
> This is a 3 termal RC osc, with a SR latch.

This one is clear.   Thanks.