Block RAM simulation VII

Page 155, XST User guide:

"XST does not support block RAM initialization in Verilog."

Why not?

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Martin Euredjian

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> "XST does not support block RAM initialization in Verilog."
>
> Why not?

Obviously because Verilog is inferior and you're being punished for your
sins.  >:_)

VHDL is the superior language, especially if you want carpel-tunnel
syndrome.


Regards,
Vinh

"Vinh Pham" wrote:

> > "XST does not support block RAM initialization in Verilog."
> >
> > Why not?
>
> Obviously because Verilog is inferior and you're being punished for your
> sins.  >:_)

Ain't that the truth!  The first part, I mean. :-)


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Martin Euredjian

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> > Obviously because Verilog is inferior and you're being punished for your
> > sins.  >:_)
>
> Ain't that the truth!  The first part, I mean. :-)

Heh heh.  Time to start a VHDL vs. Verilog flame war :_)

Page 155 of the manual...oh I see, it's talking about having XST implicitly
infer a block ram from your HDL code.  Hmm I don't know Verilog, but I would
assume it'd have the ability to initialize the values of an array, similar
to VHDL.  But even if it doesn't, you would think they can pass
initialization information through another mechanism, even perhaps through a
specially formatted comment section.

It's probably the usual "not enough people to implement all the features
we'd want; and not enough customers, or big customers, complaining about
it."

I suppose you could always go through CoreGen/explicite declaration of
BlockRAM route, and use it to initialize your ram.  The contents would be
easy to modify, when it comes to simulation at least, since it uses a text
file (.MIF) to get the values.  I'm not sure about the real hardware though.
The values might be embedded in the EDIF, which would be a bit more of a
hassle to modify.

In either case, you don't have the values handy inside of your Verilog code.
I guess you could write a Perl script that looks for a specially formattted
comment section in your Verilog, and then modify the EDIF.

Just another reason why VHDL is better ;_)

Actually I haven't used Verilog so I can't make an informed opinion...but
then again, that's never stopped people before!


Regards,
Vinh

"Vinh Pham" wrote:

> Heh heh.  Time to start a VHDL vs. Verilog flame war :_)

Don't feel like doing that.  But, clearly there are very compelling reasons
to use VHDL for synthesis if you go beyond plain-vanilla pushbutton designs.
Part of it might be due to the folks involved in writing the standards, I
learned about this in the Verilog NG ... it was like talking to someone from
another planet.

> Page 155 of the manual...oh I see, it's talking about having XST
implicitly
> infer a block ram from your HDL code.

I don't really use inference for these constructs, I instantiate explicitly.
Why would you speak Greek when you know you need to say something in French
and you can speak French?  Maybe 'cause I'm old school ... I still have my
auto-stripping electric wire-wrap gun.

No, I was just doing the usual "look through every manual to see why this
isn't working" routine.  That was the only reference I found on this
question.


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Martin Euredjian

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Hi,
I think it does.
If in ISE Project Navigator you go to Edit -> Language Templates ->
Verilog -> Component Instantiation, then you can see the way it is done (in
any of the RAM instantiation samples).
Please do correct me if I am making some mistake.
Adarsh
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:2u8Ab.66158$PY.31048@newssvr25.news.prodigy.com...
> Page 155, XST User guide:
>
> "XST does not support block RAM initialization in Verilog."
>
> Why not?
>
> -- 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_"  =  "martineu"
>
>

"Adarsh Kumar Jain" wrote:

> Verilog -> Component Instantiation, then you can see the way it is done
(in
> any of the RAM instantiation samples).

No, not instantiation for synthesis.  Simulation.  That's why the subject is
"Block RAM simulation VII".  Initializing for synthesis works very well.

If you don't see what I quoted on page 155 of your XST User Guide check the
document version.  I have 4.0, issued on 06/06/03.  It's what came with the
latest ISE update.


Also, don't use the message subject line as part of a reply, it destroys a
thread.


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Martin Euredjian

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> learned about this in the Verilog NG ... it was like talking to someone
from
> another planet.

Heh heh :_D

> I don't really use inference for these constructs, I instantiate
explicitly.
> Why would you speak Greek when you know you need to say something in
French
> and you can speak French?  Maybe 'cause I'm old school ...

You definately don't have to worry about the synthesis tools getting too
creative.  Inference can save you some typing, but spend some time with
"generics" and "generate" and you can craft a piece of reusable code that
can handle varying widths and depths.  And though I've never tried it, doing
RPMs might be easier with instantiation, since you have more control over
the structure/naming of the components.

I just use inference because of the "neato" factor when I was first learning
VHDL.

> I still have my auto-stripping electric wire-wrap gun.

Heh I think I've only used it once, during an internship.  Iy does a very
nice and neat job though.  I remember the experienced guys telling me war
stories of having to wire up an entire board, only to find out they did
something wrong under serval layers of other wiring.

> No, not instantiation for synthesis.  Simulation.  That's why the subject
is
> "Block RAM simulation VII".  Initializing for synthesis works very well.

Heh looks like I might have led Adarsh astray with my synthesis/simulation
mix up.  Oh how history repeats itself.

Hey Martin,
sorry about the subject line. I am new to this newsgroup thing...
i had an earlier version of XST. anyways, i see your point.
if it is simulation you are talking about, do you mean functional simulation
?
in that case how is XST connected to it ?
and then is it really a verilog issue ? for simulation can't you just use
the "initial"  statement ?
and for any post synthesis simulation, I think the example in language
templates works.
adarsh




"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:tlBAb.66747$aJ6.11966@newssvr25.news.prodigy.com...
> "Adarsh Kumar Jain" wrote:
>
> > Verilog -> Component Instantiation, then you can see the way it is done
> (in
> > any of the RAM instantiation samples).
>
> No, not instantiation for synthesis.  Simulation.  That's why the subject
is
> "Block RAM simulation VII".  Initializing for synthesis works very well.
>
> If you don't see what I quoted on page 155 of your XST User Guide check
the
> document version.  I have 4.0, issued on 06/06/03.  It's what came with
the
> latest ISE update.
>
>
> Also, don't use the message subject line as part of a reply, it destroys a
> thread.
>
>
> -- 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_"  =  "martineu"
>
>