Maximum Current Draw of FPGA

Austin Lesea wrote:
> Nico,
>
> You posted:
>
> "
>  datasheets lack important information on how the IOB are grouped
>  together and the clock distribution limits resulting from that
>  grouping
> "
>
> Could you be more specific?  What is it that you found to be missing?
> Which part?  Which package?  What 'important information'?  We spend
> quite a bit of time on the IO specifications, I would like to understand
> better what you felt is missing.
>
> Thank you,
>
> Austin

Well, as a user of these parts, I'll give you a few :)

[Relates to all packages I have ever used]

1. What is the maximum ICC of a particular Vcco? This relates directly
to block I/O Pd.

2. What *is* the maximum power dissipation of a particular I/O block?
I/O blocks are at the edge; as such they have their own power / heat
issues. Knowing what the maximums are would help. You could spec max
temp, provided you **thoroughly** specified the I/O block so I could
calculate it based on speed, incidentally.

3. What is the thermal distribution profile? There is core, and there
is I/O. Each has their own effect on the die, but it may well be
important to me to know that profile (it has been in the past).

4. What is the thermal profile of the Clock managers? When things get
fast, they also get hot. I need to know the power dissipation of a DCM
based on inputs and outputs.

I am sure others will drop their comments in :)

Cheers

PeteS

PeteS, let me give you a few answers:
PeteS wrote:

> 1. What is the maximum ICC of a particular Vcco? This relates directly
> to block I/O Pd.
i suppose you mean the maximum allowed Icc, an absolute max
specification.
>
> 2. What *is* the maximum power dissipation of a particular I/O block?
> I/O blocks are at the edge;
In Virtex-4 and all future Virtex parts, the I/O is no longer at the
periphery
> as such they have their own power / heat
> issues. Knowing what the maximums are would help. You could spec max
> temp, provided you **thoroughly** specified the I/O block so I could
> calculate it based on speed,
speed, strength, voltage, output loading, dc and capacitive....
>
> 3. What is the thermal distribution profile? There is core, and there
> is I/O. Each has their own effect on the die, but it may well be
> important to me to know that profile (it has been in the past).
I personally think that this is a secondary effect, given the thermal
properties of silicon. Just my opinion.
>
> 4. What is the thermal profile of the Clock managers? When things get
> fast, they also get hot. I need to know the power dissipation of a DCM
> based on inputs and outputs.
Same as above.
>
> I am sure others will drop their comments in :)
They are welcome. But let's keep the tone civilized.
Peter Alfke

Ask, and ye shall ...

See below,

Austin

-snip-

> 1. What is the maximum ICC of a particular Vcco? This relates directly
> to block I/O Pd.

What standard? What load?

Perhaps you do not have a signal integrity simultion tool?

Or Hspice?  Since it is YOUR problem, all we can do is provide with the 
tools to answer it.

We provide the IBIS and spice models you need to do this.

> 2. What *is* the maximum power dissipation of a particular I/O block?
> I/O blocks are at the edge; as such they have their own power / heat
> issues. Knowing what the maximums are would help. You could spec max
> temp, provided you **thoroughly** specified the I/O block so I could
> calculate it based on speed, incidentally.

What standard?  What load?  See answer above.

By the way, some devices have IOBs in the interior (all V4 and V5).

> 3. What is the thermal distribution profile? There is core, and there
> is I/O. Each has their own effect on the die, but it may well be
> important to me to know that profile (it has been in the past).

Are you concerned about thermal gradient?  Don't be:  we do that 
engineering so you do not have to.  Worry about maximum power 
dissipation and Tj.  There are estimation tools, and finally, better 
tools to figure power (XPower) but it requires you to have good 
simulation vectors (just like you would if you had the same ASIC 
estimation requirement).

> 4. What is the thermal profile of the Clock managers? When things get
> fast, they also get hot. I need to know the power dissipation of a DCM
> based on inputs and outputs.

Nope.  You do not.  We do the hard part, so you do not have to.

If you feel like designing ASICs, go get a job doing that.  I am not 
stopping you.  If you want to design FPGAs, submit a resume (we are hiring).

hi

seems like you problems would be solved if only LED manufactures made
surface mount LET.

= Light Emitting Transistor

not impossible, an would only draw a base current much less than
collectoer current. would be three pin and more complex production, but
would save on possible buffers.

the output dive on the fpga is limited by current heating, which is not
that high in the off or on states, but high capacitance led would
dissipate large Watts in output of fpga.

second factor is resistive loss in bond wires, have to be of a certain
size to fit so many on the chip. maybe vcc drops on chip due to heat
and cannot switch as fast reliably, so try a lower speed operation?

pulse the led output at 20% mark to 80% space as you will not notice
too much above 100Hz and save power too.

use high efficiency led, as i understand they are less than 10%
efficient anyhow.

wire half the other way with 0 = on instead of 1 = on to distribute
power drain between + and - rails.

cheers

http://indi.joox.net

OFSIC in design, at documentation interface stage. then we shall move
onto code.

i am in the market for employment.

london area, min 500 uk pound per wk. pro rata 40 hrs.

parttime prefered, about 20hrs per wk.

can only telework if get full time internet, and rented place.

c.v. e.g. http://indi.joox.net

cheers

Austin Lesea <austin@xilinx.com> wrote:

>Nico,
>
>You posted:
>
>"
> datasheets lack important information on how the IOB are grouped
> together and the clock distribution limits resulting from that
> grouping
>"
>
>Could you be more specific?  What is it that you found to be missing?
>Which part?  Which package?  What 'important information'?  We spend
>quite a bit of time on the IO specifications, I would like to understand
>better what you felt is missing.

Mostly Spartan 3:
- Resource sharing on IOBs, multipliers and blockrams
- Internal routing of local IOB clocks (for DDR memory purposes)
- Minimum and maximum delays, setup / hold for all elements. Now I
have to use the timing analyzer to get these numbers.
- Other stuff I don't know about -yet-

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Rene Tschaggelar schrieb:
> Nevo wrote:
>> I am planning on attaching a green LED to each of the 96 I/O pins
>> exposed on the connectors through 390 ohm resistors.

> LEDs do not need 20mA, in most cases, 1mA is
> clearly visible.

Green LED on 3.3V over 390R is more like 3mA, not 20mA.

I = (3.3V - 2.1V)/390R < 3.1mA


Also:
I prefer to connect the positive end of the LED to VCC end pull
the other end low by the FPGA. This way the stronger NMOS transistors
are used. GTL drivers of Spartan-2 sink 200mA.

Kolja Sulimma

On 15 Aug 2006 16:36:48 -0700, "Peter Alfke" <peter@xilinx.com> wrote:


>> 3. What is the thermal distribution profile? There is core, and there
>> is I/O. Each has their own effect on the die, but it may well be
>> important to me to know that profile (it has been in the past).
>I personally think that this is a secondary effect, given the thermal
>properties of silicon. Just my opinion.

This is getting to be quite a big area; see Gradient/Firebolt
(http://www.gradient-da.com/),  Apache/Sahara
(http://www.apache-da.com/html/products_solutions/sahara.htm#CHALLENGE),
and so on. The spin is that you have to control for temperature
distribution across your chip at sub-90nm.

You've got an interesting problem here, since you don't know how your
chips are going to be used.

Evan

Nico,

Thank you.  Steve Knapp reads this newsgroup for the Spartan division,
and I am sure he will appreciate your comments.  I am part of the Virtex
team, so as these may also apply there, I will make sure the data sheet
folks get this feedback, also.

I know that we cover quite a bit of what you listed in our user guides:
V4 - http://direct.xilinx.com/bvdocs/userguides/ug070.pdf
V5 - http://direct.xilinx.com/bvdocs/userguides/ug190.pdf

Since Spartan 3 does not have a users guide, perhaps this is part of the
problem?  3E also does not have a users guide.  Not sure why that
division didn't do user's guides; they are a separate business group,
and they need to make their customers happy, just as we do.

Thanks for the constructive feedback,

Austin

Nico Coesel wrote:
> Austin Lesea <austin@xilinx.com> wrote:
> 
>> Nico,
>>
>> You posted:
>>
>> "
>> datasheets lack important information on how the IOB are grouped
>> together and the clock distribution limits resulting from that
>> grouping
>> "
>>
>> Could you be more specific?  What is it that you found to be missing?
>> Which part?  Which package?  What 'important information'?  We spend
>> quite a bit of time on the IO specifications, I would like to understand
>> better what you felt is missing.
> 
> Mostly Spartan 3:
> - Resource sharing on IOBs, multipliers and blockrams
> - Internal routing of local IOB clocks (for DDR memory purposes)
> - Minimum and maximum delays, setup / hold for all elements. Now I
> have to use the timing analyzer to get these numbers.
> - Other stuff I don't know about -yet-
>