Large Spartan3 vs. Small V5

So is Xilinx working on another budget-line FPGA? Or are they intending
that small V5 chips replace the Spartan line altogether? What's their
next budget chip with the new LUT structure and when can I look for it?

According to Xilinx's website, the Spartan-3E line is for gate-centric
uses and goes up to 1.2M gates. Yeah. Huge.

I just finished a project that uses 4.5M gates (so says the MRP) on
each of eight 2v6000 chips. It's only using 1/3 the block RAM and none
of the MUL blocks on any chip. It only accesses DRAM from one chip. I
want that project on cheap hardware. What chips would you recommend for
this? By cheap I mean $40/chip, not $2000/chip.

On 2006-08-15, Brannon <brannonking@yahoo.com> wrote:
> I just finished a project that uses 4.5M gates (so says the MRP) on
> each of eight 2v6000 chips. It's only using 1/3 the block RAM

Maybe that's the problem.  Can you move any of your storage into block
ram and do serial processing?

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Brannon wrote:
> So is Xilinx working on another budget-line FPGA? Or are they intending
> that small V5 chips replace the Spartan line altogether? What's their
> next budget chip with the new LUT structure and when can I look for it?
>
> According to Xilinx's website, the Spartan-3E line is for gate-centric
> uses and goes up to 1.2M gates. Yeah. Huge.
>
> I just finished a project that uses 4.5M gates (so says the MRP) on
> each of eight 2v6000 chips. It's only using 1/3 the block RAM and none
> of the MUL blocks on any chip. It only accesses DRAM from one chip. I
> want that project on cheap hardware. What chips would you recommend for
> this? By cheap I mean $40/chip, not $2000/chip.

Howdy Brannon,

What is your target production date?  Next week (need to use S3 or V4)
or early next year (in which case, you can consider *some* V5's)?  I
assume that since you are considering V5, you don't have any
restrictions on your power rail(s), and they can be made to be
relatively clean.  Life-span of the product and number of devices
needed per year would probably also figure into how much it makes sense
to stay in standard FPGA vs. an easy path approach.

Lastly, "4.5M gates" doesn't mean much.  Is that 55k LUTS?

My WAG is that your least expensive alternative is probably  an
XC3S4000.

Good luck,

   Marc

Here is a shot at it,

See below,

Austin

-snip-

> So is Xilinx working on another budget-line FPGA?

Yes.  Always.  It is "our business."

  Or are they intending
> that small V5 chips replace the Spartan line altogether?

No.  We sorted that out, the Virtex line is no longer interested in 
"small" parts.

  What's their
> next budget chip with the new LUT structure and when can I look for it?

I can't tell you something like that!  One thing you can always count 
on:  Moore's Law.  Is 65nm smaller and cheaper?  Yes.  And 45nm, yes 
again.  And so on.

> According to Xilinx's website, the Spartan-3E line is for gate-centric
> uses and goes up to 1.2M gates. Yeah. Huge.

For some, yes, others not.  It is all about marketing.  Sell to the ones 
who have the money.  Cost of mask set, etc.  How many did you want?

> I just finished a project that uses 4.5M gates (so says the MRP) on
> each of eight 2v6000 chips. It's only using 1/3 the block RAM and none
> of the MUL blocks on any chip. It only accesses DRAM from one chip. I
> want that project on cheap hardware.

Congratulations on your accomplishment...

  What chips would you recommend for
> this? By cheap I mean $40/chip, not $2000/chip.

Well, four 2V6000s is now proabably replaced by 5VLX220.  That doesn't 
include any intelligent re-targeting to structures that are better 
suited (ie more compact) or design changes to fit it into a smaller 
device. 5VLX220 will not be "introduced" until later (just keep watch on 
the announcements).

As for less than $40 (for a LX220), well, that doesn't seem likely, even 
at 65nm.

Maybe next time?  From the Virtex 1000, to the Spartan 3S1000, the price 
to the user has diminshed by more than two decades (for the same, or 
more, logic).

Brannon wrote:
> So is Xilinx working on another budget-line FPGA? Or are they intending
> that small V5 chips replace the Spartan line altogether? What's their
> next budget chip with the new LUT structure and when can I look for it?
> 
> According to Xilinx's website, the Spartan-3E line is for gate-centric
> uses and goes up to 1.2M gates. Yeah. Huge.
> 
> I just finished a project that uses 4.5M gates (so says the MRP) on
> each of eight 2v6000 chips. It's only using 1/3 the block RAM and none
> of the MUL blocks on any chip. It only accesses DRAM from one chip. I
> want that project on cheap hardware. What chips would you recommend for
> this? By cheap I mean $40/chip, not $2000/chip.

Since you do not use MULs and only little BRAM, the V4LX series would 
make sense - more logic, much fewer specialized (BRAM/DSP) resources and 
less expensive than their V2 equivalents... but nowhere near $40/chip 
though.

Unless there are specific reasons why you need the 3E, the plain '3' go 
up to ~5M gates but even that still costs way more than $40/chip: I 
checked out prices on avnet, XC3S5000-4FG1156C = $390 each.

> > I just finished a project that uses 4.5M gates (so says the MRP) on
> > each of eight 2v6000 chips. It's only using 1/3 the block RAM
>
> Maybe that's the problem.  Can you move any of your storage into block
> ram and do serial processing?

This project is to outrun serial processors, which it does by doing
lots in parallel. It is not doing much in the way of storage. Think
software acceleration, not ASIC prototyping.

> What is your target production date?  Next week (need to use S3 or V4)
> or early next year (in which case, you can consider *some* V5's)?  I
> assume that since you are considering V5, you don't have any
> restrictions on your power rail(s), and they can be made to be
> relatively clean.  Life-span of the product and number of devices
> needed per year would probably also figure into how much it makes sense
> to stay in standard FPGA vs. an easy path approach.
The boards with 2v6000 chips are already in production. I was thinking
of this as a next-gen version of the hardware for somewheres about 8
months from now.

> Lastly, "4.5M gates" doesn't mean much.  Is that 55k LUTS?

It uses 49k LUTS and the same number of FFs.

> My WAG is that your least expensive alternative is probably  an
> XC3S4000.

I probably need the 5000, and they are not as cheap as I'd like though
significantly cheaper than 2v6000.

> Unless there are specific reasons why you need the 3E, the plain '3' go
> up to ~5M gates but even that still costs way more than $40/chip: I
> checked out prices on avnet, XC3S5000-4FG1156C = $390 each.

The series 3 are .13 micron, true? Is that why they're (debateably)
expensive?

> I probably need the 5000, and they are not as cheap as I'd like though
> significantly cheaper than 2v6000.

Well, after looking at the charts again, maybe a 3s4000 would do it.
Even the 2000 model is reasonably large. Unfortunately, the Webpack
tool doesn't support any of those larger Spartan 3 chips. I had been
hoping to find a chip solution that would allow product customers to
customize their gateware using Webpack (because it's free for them).

Brannon wrote:
>> I probably need the 5000, and they are not as cheap as I'd like though
>> significantly cheaper than 2v6000.
> 
> Well, after looking at the charts again, maybe a 3s4000 would do it.
> Even the 2000 model is reasonably large. Unfortunately, the Webpack
> tool doesn't support any of those larger Spartan 3 chips. I had been
> hoping to find a chip solution that would allow product customers to
> customize their gateware using Webpack (because it's free for them).

Altera's Cyclone II family is fully supported by free tools and the 
largest (EP2C70) is about 68k LUT, much more than the 3S5000.

I don't know how the pricing compare though.


Tommy