Large Spartan3 vs. Small V5

Brannon wrote:

>>Unless there are specific reasons why you need the 3E, the plain '3' go
>>up to ~5M gates but even that still costs way more than $40/chip: I
>>checked out prices on avnet, XC3S5000-4FG1156C = $390 each.
>>    
>>
>
>The series 3 are .13 micron, true? Is that why they're (debateably)
>expensive?
>
>  
>
spartan3 (and s3E) is  90 nm
Aurash

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/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
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Brannon wrote:
>> Unless there are specific reasons why you need the 3E, the plain '3' go
>> up to ~5M gates but even that still costs way more than $40/chip: I
>> checked out prices on avnet, XC3S5000-4FG1156C = $390 each.
> 
> The series 3 are .13 micron, true? Is that why they're (debateably)
> expensive?

IIRC, the 3E is the 'Economy' series, the 3L is the 'Low-Power' series 
and plain 3 is standard parts. Like others said, they all are 90nm.

BTW, if you are really wasting BRAMs, you could tell your synthesis 
tools to map logic into BRAM. If the older Vxxxx have anywhere near the 
V2P's BRAM-to-logic ratio, this would free up a bunch of LUT/FFs.

Me, I am holding my breath until the V5SXes come out - I am hoping for 
12xRocketIO for the price of 8 on V4.

> Altera's Cyclone II family is fully supported by free tools and the
> largest (EP2C70) is about 68k LUT, much more than the 3S5000.
>
> I don't know how the pricing compare though.

I think you may have proposed a great plan. Their prices range from
$125 to $300 for their 672 pin chips (according to their website).
That's still three times what I had been hoping for, but maybe I could
make that work. And it is 25% cheaper than Xilinx. Can I get these
Cyclone II chips for less than that through some other dealer?

Brannon wrote:
> I think you may have proposed a great plan. Their prices range from
> $125 to $300 for their 672 pin chips (according to their website).
> That's still three times what I had been hoping for, but maybe I could
> make that work. And it is 25% cheaper than Xilinx. Can I get these
> Cyclone II chips for less than that through some other dealer?

Glad to be of (self-) service :-) I might be a taker if it has big
enough devices (insert my usual plea for lots of RLDRAM II memory).

Tommy

In article <1155685199.857669.180670@74g2000cwt.googlegroups.com>,
Brannon <brannonking@yahoo.com> wrote:
>So is Xilinx working on another budget-line FPGA? Or are they intending
>that small V5 chips replace the Spartan line altogether? What's their
>next budget chip with the new LUT structure and when can I look for it?
>
>According to Xilinx's website, the Spartan-3E line is for gate-centric
>uses and goes up to 1.2M gates. Yeah. Huge.
>
>I just finished a project that uses 4.5M gates (so says the MRP) on
>each of eight 2v6000 chips. It's only using 1/3 the block RAM and none
>of the MUL blocks on any chip. It only accesses DRAM from one chip. I
>want that project on cheap hardware.

Is it impossible to make the project use 1.25M gates on each of
thirty-two 3S1500 chips?  

http://www.hyperelliptic.org/tanja/SHARCS/talks06/copa_sharcs.pdf

is the sort of hardware that I imagine targetting when contemplating
cheap FPGA approaches to problems.

Tom

Brannon

On current technology you would be very lucky to make $40/chip mark for
something the size of a 2V6000 unless you have a very high volume. Even
then I'm dubious.

However it is worth examining your design to see if it can be crushed
to allow smaller cheaper parts to be used. I have seen designs reduced
by 40-50% in some cases by a good designer. Playing with tool settings
can give you something but the best I have seen is in the order of
10-15% reduction by this approach.

Another thing to consider is sharing of resources to reduce size e.g. a
multiplier servicing 2 data streams in a time muxed fashion.

Also for the brew is the fact that the biggest devices come at a
premium and several smaller devices of the equivalent logic size may be
cheaper.

It is also worth looking at the ram to logic ration of the chip you
use. RAM is a relatively expensive resource in a FPGA so using a FPGA
that is less memory rich may bring benefits. Typically the lower end
families have a lower ram/logic ratio. Even within families you will
find variations in the ration so choosing an appropraite size may help
cost too.

John Adair
Enterpoint Ltd.


Brannon wrote:
> So is Xilinx working on another budget-line FPGA? Or are they intending
> that small V5 chips replace the Spartan line altogether? What's their
> next budget chip with the new LUT structure and when can I look for it?
>
> According to Xilinx's website, the Spartan-3E line is for gate-centric
> uses and goes up to 1.2M gates. Yeah. Huge.
>
> I just finished a project that uses 4.5M gates (so says the MRP) on
> each of eight 2v6000 chips. It's only using 1/3 the block RAM and none
> of the MUL blocks on any chip. It only accesses DRAM from one chip. I
> want that project on cheap hardware. What chips would you recommend for
> this? By cheap I mean $40/chip, not $2000/chip.

Brannon wrote:
> > Altera's Cyclone II family is fully supported by free tools and the
> > largest (EP2C70) is about 68k LUT, much more than the 3S5000.
> >
> > I don't know how the pricing compare though.
>
> I think you may have proposed a great plan. Their prices range from
> $125 to $300 for their 672 pin chips (according to their website).
> That's still three times what I had been hoping for, but maybe I could
> make that work. And it is 25% cheaper than Xilinx. Can I get these
> Cyclone II chips for less than that through some other dealer?

I was talking to a rep the other day and he pointed out that "there is
no minimum pricing for FPGAs".  Now we know that is not really true,
but the point is that if you speak with the disti or the manufacturers
account manager, they will be willing to "bid" on your business much
more so than other semi manufacturers.  There seems to be a very high
markup on FPGAs and if you buy in any volume they will give you some
good pricing.  I have seen this first hand where I was given 50,000
piece pricing for 1,000 piece quantities in order to get the design
win.

So don't worry about web pricing, it is typically not very good.  Get
the disti involved and you can get some much better pricing.

Thomas Womack wrote:
>> I just finished a project that uses 4.5M gates (so says the MRP) on
>> each of eight 2v6000 chips. It's only using 1/3 the block RAM and none
>> of the MUL blocks on any chip. It only accesses DRAM from one chip. I
>> want that project on cheap hardware.
> 
> Is it impossible to make the project use 1.25M gates on each of
> thirty-two 3S1500 chips?  
> 
> http://www.hyperelliptic.org/tanja/SHARCS/talks06/copa_sharcs.pdf
> 
> is the sort of hardware that I imagine targetting when contemplating
> cheap FPGA approaches to problems.

The more chips you have, the more IOs you need to stitch them together 
unless the data dependencies are highly linear, clean and somewhat 
minimalist. Otherwise peak attainable performance quickly becomes IO-bound.

In the case of code-breaking applications, as long as you pick FPGAs 
large enough to contain at least one instance of the code-breaking unit, 
you will not need to worry about interconnects. The rest is simply a 
matter of setting performance targets, selecting an FPGA family then 
cost-optimize the device count, size (number of code-breaking units per 
FPGA vs device cost) and speed grade - code-breaking is generally so 
parallelizable that there is very little to no performance gain between 
a single large-scale system and N N-times as slow smaller-scale ones.