Hi all, I'm working on an FPGA implementation of an image processing algorithm. I'll be using the ML401 to do the job which has DDR memory and a VGA port to output the image directly on screen. Should I go with a microblaze solution? EDK comes with DDR and VGA controllers for this board, however I'm not at all familiar with it regarding the buses and stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the memory controller and I've also found a VGA/LCD display module on opencores.org. So both solutions seem viable to me (or do they not?), which path should I choose? Please comment. Thanks!
EDK vs. ISE for image processing
Started by ●August 17, 2006
Reply by ●August 17, 20062006-08-17
"fpganovice" <alecwei@gmail.com> wrote in message news:1155833480.035692.283020@b28g2000cwb.googlegroups.com...> Hi all, > > I'm working on an FPGA implementation of an image processing algorithm. > I'll be using the ML401 to do the job which has DDR memory and a VGA > port to output the image directly on screen. Should I go with a > microblaze solution? EDK comes with DDR and VGA controllers for this > board, however I'm not at all familiar with it regarding the buses and > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > memory controller and I've also found a VGA/LCD display module on > opencores.org. So both solutions seem viable to me (or do they not?), > which path should I choose? Please comment. Thanks! >If you don't need a CPU, then you don't need EDK either. If you do need a CPU, it is much easier to use EDK. However, if you decide not to use EDK you will probably have to spend more time interfacing your pieces, e.g. the opencores VGA controller probably needs a Wishbone bus... On the side note, it might be worth mentioning that some of the EDK ready-to-use cores are behind performance-wise from what is generally available, e.g. I believe MIG allows for faster DDRAM interfaces than you could achieve by using any of the EDK memory controllers. /Mikhail
Reply by ●August 17, 20062006-08-17
Hi Mikhail, Thanks for your reply. The VGA core does use a Wishbone bus, and it has built-in Wishbone master and slave interfaces. It seems like I just need to set some registers through the slave and get access to external memory through the master. Therefore I was thinking those interfaces could connect with my FPGA hardware directly, or do I still need something to talk to the core? Thanks again. MM wrote:> "fpganovice" <alecwei@gmail.com> wrote in message > news:1155833480.035692.283020@b28g2000cwb.googlegroups.com... > > Hi all, > > > > I'm working on an FPGA implementation of an image processing algorithm. > > I'll be using the ML401 to do the job which has DDR memory and a VGA > > port to output the image directly on screen. Should I go with a > > microblaze solution? EDK comes with DDR and VGA controllers for this > > board, however I'm not at all familiar with it regarding the buses and > > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > > memory controller and I've also found a VGA/LCD display module on > > opencores.org. So both solutions seem viable to me (or do they not?), > > which path should I choose? Please comment. Thanks! > > > > If you don't need a CPU, then you don't need EDK either. If you do need a > CPU, it is much easier to use EDK. However, if you decide not to use EDK you > will probably have to spend more time interfacing your pieces, e.g. the > opencores VGA controller probably needs a Wishbone bus... > > On the side note, it might be worth mentioning that some of the EDK > ready-to-use cores are behind performance-wise from what is generally > available, e.g. I believe MIG allows for faster DDRAM interfaces than you > could achieve by using any of the EDK memory controllers. > > > /Mikhail
Reply by ●August 17, 20062006-08-17
"fpganovice" <alecwei@gmail.com> wrote in message news:1155836380.092010.183830@m73g2000cwd.googlegroups.com...> Hi Mikhail, > > Thanks for your reply. The VGA core does use a Wishbone bus, and it > has built-in Wishbone master and slave interfaces. It seems like I > just need to set some registers through the slave and get access to > external memory through the master. Therefore I was thinking those > interfaces could connect with my FPGA hardware directly, or do I still > need something to talk to the core? >Depending on what you mean under "directly". The MIG memory controller is not aware of Wishbone... So, you will need to do a Wishbone interface for it, however simple. The same is true for the other direction... /Mikhail
Reply by ●August 18, 20062006-08-18
Hi fpganovice, Forget about MicroBlaze, you will never get the desired speed. Image processing should be done in logic ONLY. Try to figure out how you can serialize your processing algorithm to work pixel-to-pixel. This way you probably won't even need a DDR. There is also a Xilinx thing called Multi Port Memory Controller 2 which has a fast interface to DDR, PowePC and GigaLAN. PLB_LCD (native LCD) controller is also included in the project cores. The only drawback is that it consumes a lot of logic, which you can use for image processing. Cheers, Guru fpganovice wrote:> Hi all, > > I'm working on an FPGA implementation of an image processing algorithm. > I'll be using the ML401 to do the job which has DDR memory and a VGA > port to output the image directly on screen. Should I go with a > microblaze solution? EDK comes with DDR and VGA controllers for this > board, however I'm not at all familiar with it regarding the buses and > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > memory controller and I've also found a VGA/LCD display module on > opencores.org. So both solutions seem viable to me (or do they not?), > which path should I choose? Please comment. Thanks!
Reply by ●August 18, 20062006-08-18
Oh yes, I forgot one more thing: FPGA->VGA OPB bus driver was included in the Spartan3 starter kit Xpong project - opb_color_video_ctrl_v1_00_a. Cheers, Guru fpganovice wrote:> Hi all, > > I'm working on an FPGA implementation of an image processing algorithm. > I'll be using the ML401 to do the job which has DDR memory and a VGA > port to output the image directly on screen. Should I go with a > microblaze solution? EDK comes with DDR and VGA controllers for this > board, however I'm not at all familiar with it regarding the buses and > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > memory controller and I've also found a VGA/LCD display module on > opencores.org. So both solutions seem viable to me (or do they not?), > which path should I choose? Please comment. Thanks!
Reply by ●August 18, 20062006-08-18
Does a ML301 has a video DAC? Opencores VGA/LCD controller needs three 8 bit DACs!!!!. Guru Guru wrote:> Oh yes, I forgot one more thing: > > FPGA->VGA OPB bus driver was included in the Spartan3 starter kit Xpong > project - opb_color_video_ctrl_v1_00_a. > > Cheers, > > Guru > > > fpganovice wrote: > > Hi all, > > > > I'm working on an FPGA implementation of an image processing algorithm. > > I'll be using the ML401 to do the job which has DDR memory and a VGA > > port to output the image directly on screen. Should I go with a > > microblaze solution? EDK comes with DDR and VGA controllers for this > > board, however I'm not at all familiar with it regarding the buses and > > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > > memory controller and I've also found a VGA/LCD display module on > > opencores.org. So both solutions seem viable to me (or do they not?), > > which path should I choose? Please comment. Thanks!
Reply by ●August 18, 20062006-08-18
Microblaze is not so fast but why not to design microblaze plus some hardware accelerators. It could be fast enough and easy to design, I suppose. /Wayne Guru wrote:> Hi fpganovice, > > Forget about MicroBlaze, you will never get the desired speed. Image > processing should be done in logic ONLY. Try to figure out how you can > serialize your processing algorithm to work pixel-to-pixel. This way > you probably won't even need a DDR. > > There is also a Xilinx thing called Multi Port Memory Controller 2 > which has a fast interface to DDR, PowePC and GigaLAN. PLB_LCD (native > LCD) controller is also included in the project cores. The only > drawback is that it consumes a lot of logic, which you can use for > image processing. > > Cheers, > > Guru > > fpganovice wrote: > > Hi all, > > > > I'm working on an FPGA implementation of an image processing algorithm. > > I'll be using the ML401 to do the job which has DDR memory and a VGA > > port to output the image directly on screen. Should I go with a > > microblaze solution? EDK comes with DDR and VGA controllers for this > > board, however I'm not at all familiar with it regarding the buses and > > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > > memory controller and I've also found a VGA/LCD display module on > > opencores.org. So both solutions seem viable to me (or do they not?), > > which path should I choose? Please comment. Thanks!
Reply by ●August 18, 20062006-08-18
Hi Wayne, This is what I was originally thinking. I already have a VHDL module for image processing pixel-by-pixel. So I was thinking of integrating it with the microblaze and use the DDR and VGA controllers that come with the microblaze design. quickwayne@gmail.com wrote:> Microblaze is not so fast but why not to design microblaze plus some > hardware accelerators. It could be fast enough and easy to design, I > suppose. > > /Wayne > > Guru wrote: > > Hi fpganovice, > > > > Forget about MicroBlaze, you will never get the desired speed. Image > > processing should be done in logic ONLY. Try to figure out how you can > > serialize your processing algorithm to work pixel-to-pixel. This way > > you probably won't even need a DDR. > > > > There is also a Xilinx thing called Multi Port Memory Controller 2 > > which has a fast interface to DDR, PowePC and GigaLAN. PLB_LCD (native > > LCD) controller is also included in the project cores. The only > > drawback is that it consumes a lot of logic, which you can use for > > image processing. > > > > Cheers, > > > > Guru > > > > fpganovice wrote: > > > Hi all, > > > > > > I'm working on an FPGA implementation of an image processing algorithm. > > > I'll be using the ML401 to do the job which has DDR memory and a VGA > > > port to output the image directly on screen. Should I go with a > > > microblaze solution? EDK comes with DDR and VGA controllers for this > > > board, however I'm not at all familiar with it regarding the buses and > > > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > > > memory controller and I've also found a VGA/LCD display module on > > > opencores.org. So both solutions seem viable to me (or do they not?), > > > which path should I choose? Please comment. Thanks!
Reply by ●August 18, 20062006-08-18
I'm using an ML401. It does have a DAC from analog device. Guru wrote:> Does a ML301 has a video DAC? Opencores VGA/LCD controller needs three > 8 bit DACs!!!!. > > Guru > > > > Guru wrote: > > Oh yes, I forgot one more thing: > > > > FPGA->VGA OPB bus driver was included in the Spartan3 starter kit Xpong > > project - opb_color_video_ctrl_v1_00_a. > > > > Cheers, > > > > Guru > > > > > > fpganovice wrote: > > > Hi all, > > > > > > I'm working on an FPGA implementation of an image processing algorithm. > > > I'll be using the ML401 to do the job which has DDR memory and a VGA > > > port to output the image directly on screen. Should I go with a > > > microblaze solution? EDK comes with DDR and VGA controllers for this > > > board, however I'm not at all familiar with it regarding the buses and > > > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > > > memory controller and I've also found a VGA/LCD display module on > > > opencores.org. So both solutions seem viable to me (or do they not?), > > > which path should I choose? Please comment. Thanks!
