Warningmessage in ISE

Hi there

When I synthesis my design I get some warning messages.

A strange on is this: <<WARNING:Xst:647 - Input <clk> is never used.>>

It is declared in the Entity:
entity RS232 is
    Port (
				reset			: in std_logic;
				clk 			: in  STD_LOGIC;
				rx 				: in  STD_LOGIC;
				PData 		: out  STD_LOGIC_VECTOR (7 downto 0);
				PDataAcc 	: out  STD_LOGIC);
end RS232;

It is used in a process:
SmallClkPros : process(clk, reset)
		begin
...
...
end process SmallClkPros;

Why do I get this warning?

Raymond

Raymond wrote:
> Hi there
> 
> When I synthesis my design I get some warning messages.
> 
> A strange on is this: <<WARNING:Xst:647 - Input <clk> is never used.>>
> 
> It is declared in the Entity:
> entity RS232 is
>     Port (
> 				reset			: in std_logic;
> 				clk 			: in  STD_LOGIC;
> 				rx 				: in  STD_LOGIC;
> 				PData 		: out  STD_LOGIC_VECTOR (7 downto 0);
> 				PDataAcc 	: out  STD_LOGIC);
> end RS232;
> 
> It is used in a process:
> SmallClkPros : process(clk, reset)
> 		begin
> ...
> ...
> end process SmallClkPros;
> 
> Why do I get this warning?
> 
> Raymond
> 

It simply means you are not using the signal in a synthesisable 
statement. Process signal enumerations are only relevant for simulation. 
Clock signals must be used in "if rising_edge(clk) then" statements to 
infer FFs in synthesis and extra conditions are used to infer 
clock-enable and mux logic.

-- 
Daniel Sauvageau
moc.xortam@egavuasd
Matrox Graphics Inc.
1155 St-Regis, Dorval, Qc, Canada
514-822-6000

> A strange on is this: <<WARNING:Xst:647 - Input <clk> is never used.>>

I am going to assume that you have something
in your process that uses clk. In that case,
the next likely candidate is that the synthesis
tool has found no outgoing signals in that process,
that is, signals that connect to output pins, or
signals that connect to signals that go to output pins,
and has therefore been eliminated. I believe that
causes this warning in Xilinx ISE.

Brad Smallridge
aivision

Brad Smallridge skrev:
> > A strange on is this: <<WARNING:Xst:647 - Input <clk> is never used.>>
>
> I am going to assume that you have something
> in your process that uses clk. In that case,
> the next likely candidate is that the synthesis
> tool has found no outgoing signals in that process,
> that is, signals that connect to output pins, or
> signals that connect to signals that go to output pins,
> and has therefore been eliminated. I believe that
> causes this warning in Xilinx ISE.
>
> Brad Smallridge
> aivision

Actually, the process generates an other "controllable" clock that
clocks an other process that has signals that is connected to other
signals that in turn goes to output pins. (puh)

Raymond

I see that to run a process from an other process can be avoided (Like
I do now) so I tried to put everything in the same process, same
warnings.

////////////////////////// Warnings //////////////////////
WARNING:Xst:647 - Input <clk> is never used.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:647 - Input <rx> is never used.
WARNING:Xst:646 - Signal <SmallCountReg> is assigned but never used.
WARNING:Xst:646 - Signal <RPData> is assigned but never used.
WARNING:Xst:646 - Signal <CountReg> is assigned but never used.
////////////////////////////////////////////////////////////////

////////////////////////// CODE ///////////////////////////
entity RS232 is
    Port (
				reset			: in std_logic;
				clk 			: in  STD_LOGIC;
				rx 				: in  STD_LOGIC;
				PData 		: out  STD_LOGIC_VECTOR (7 downto 0);
				PDataAcc 	: out  STD_LOGIC);
end RS232;

architecture Behavioral of RS232 is

	signal RPData 		  : std_logic_vector(9 downto 0);
	signal CountReg          : std_logic_vector(12 downto 0);
	signal SmallCountReg  : std_logic_vector(3 downto 0);
	signal RPDataAcc	: std_logic;

begin

	SmallClkPros : process(clk, reset)
		begin
			if(reset <= '1') then
				CountReg 	 <= conv_std_logic_vector(0, 13);
				SmallCountReg <= conv_std_logic_vector(0, 4);
				RPData		  <= conv_std_logic_vector(0, 10);
				RPDataAcc 	<= '0';

			elsif(rising_edge(clk)) then
				if(rx = '0' and CountReg < conv_std_logic_vector(2604, 13) and
					SmallCountReg = conv_std_logic_vector(0, 4)) then
						CountReg <= CountReg + 1;
						RPDataAcc <= '0';

				elsif(rx = '0' and CountReg = conv_std_logic_vector(2604, 13) and
					SmallCountReg = conv_std_logic_vector(0, 4)) then
						CountReg <= CountReg + 1;
						SmallCountReg <= SmallCountReg + 1;
						RPData(0) <= rx;
						RPData(9 downto 1) <= RPData(8 downto 0);

				elsif(CountReg < conv_std_logic_vector(2604, 13) and
					SmallCountReg < conv_std_logic_vector(10, 4) and
					SmallCountReg > conv_std_logic_vector(0, 4)) then
						CountReg <= CountReg + 1;
						SmallCountReg <= SmallCountReg + 1;
						RPData(0) <= rx;
						RPData(9 downto 1) <= RPData(8 downto 0);

				elsif(CountReg < conv_std_logic_vector(5208, 13) and
				 SmallCountReg > conv_std_logic_vector(0, 4) and
				 SmallCountReg < conv_std_logic_vector(10, 4)) then
				 		CountReg <= CountReg + 1;

				elsif(CountReg = conv_std_logic_vector(5208, 13) and
					SmallCountReg > conv_std_logic_vector(0, 4) and
					SmallCountReg < conv_std_logic_vector(10, 4)) then
						CountReg <= conv_std_logic_vector(0, 13);

				elsif(CountReg = conv_std_logic_vector(5208, 13) and
					SmallCountReg = conv_std_logic_vector(10, 4)) then
						SmallCountReg <= conv_std_logic_vector(0, 4);
						CountReg 	<= conv_std_logic_vector(0, 13);
						RPDataAcc	<= '1';
				end if;
			end if;
		end process SmallClkPros;

	PData <= RPData(8 downto 1);
	PDataAcc <= RPDataAcc;

end Behavioral;

////////////////////////////////////////////////////////////////////////

Raymond

On 20 Aug 2006 12:33:20 -0700, "Raymond" <raybakk@yahoo.no> wrote:


>			if(reset <= '1') then

did you mean   reset = '1'  here ??

Gerhard

Gerhard Hoffmann wrote:
> On 20 Aug 2006 12:33:20 -0700, "Raymond" <raybakk@yahoo.no> wrote:
>
>
> >			if(reset <= '1') then
>
> did you mean   reset = '1'  here ??
>
> Gerhard

Gerhard, Thank you Thank you Thank you :) :) :)

I have been completly blind!!!

Raymond