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ModelSim SE PLUS 6.1B. Problem to simulate RocketIO in GT_CUSTOM mode

Started by Unknown ●August 22, 2006
Modelsim report is:

# Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl
# //  ModelSim SE 6.1b Sep  8 2005
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do {test_clock.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
# -- Compiling module stm4ser
#
# Top level modules:
# 	stm4ser
# Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
# -- Compiling module dcm1
#
# Top level modules:
# 	dcm1
# Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
# -- Compiling module clock
#
# Top level modules:
# 	clock
# Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
# -- Compiling module test_clock
#
# Top level modules:
# 	test_clock
# Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
# -- Compiling module glbl
#
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps test_clock
glbl
# Loading work.test_clock
# Loading work.clock
# Loading work.dcm1
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.BUFG
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.IBUFG
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.DCM
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_divide_by_2
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_maximum_period_check
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_lost
# Loading work.stm4ser
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_CUSTOM
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT
# Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT_BIT
# Loading work.glbl
# ** Warning: (vsim-PLI-3003)
C:/Xilinx/verilog/mti_se/unisims_ver/unisims_ver_SmartWrapper_source.v(18339):
[TOFD] - System task or function '$lm_model' is not defined.
#         Region:
/test_clock/UUT/module1/GT_CUSTOM_INST/gt_1/gt_swift_1/I1
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
# No errors or warnings.
# Break at test_clock.tfw line 82
# Simulation Breakpoint: Break at test_clock.tfw line 82
# MACRO ./test_clock.fdo PAUSED at line 17

In this report I'm not andestend warning. All off signals from RocketIO
module is x-state. But all of oter modules simulate succes.

:) And sorry my very bad english
Reply by Jim Wu ●August 22, 20062006-08-22
Have you checked AR  22214?

http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=22214


HTH,
Jim
http://home.comcast.net/~jimwu88/tools/

axalay@gmail.com wrote:

> Modelsim report is:
>
> # Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl
> # //  ModelSim SE 6.1b Sep  8 2005
> # //
> # //  Copyright Mentor Graphics Corporation 2005
> # //              All Rights Reserved.
> # //
> # //  THIS WORK CONTAINS TRADE SECRET AND
> # //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
> # //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
> # //  AND IS SUBJECT TO LICENSE TERMS.
> # //
> # do {test_clock.fdo}
> # ** Warning: (vlib-34) Library already exists at "work".
> # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> # -- Compiling module stm4ser
> #
> # Top level modules:
> # 	stm4ser
> # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> # -- Compiling module dcm1
> #
> # Top level modules:
> # 	dcm1
> # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> # -- Compiling module clock
> #
> # Top level modules:
> # 	clock
> # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> # -- Compiling module test_clock
> #
> # Top level modules:
> # 	test_clock
> # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> # -- Compiling module glbl
> #
> # Top level modules:
> # 	glbl
> # vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps test_clock
> glbl
> # Loading work.test_clock
> # Loading work.clock
> # Loading work.dcm1
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.BUFG
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.IBUFG
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.DCM
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_divide_by_2
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_maximum_period_check
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_lost
> # Loading work.stm4ser
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_CUSTOM
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT
> # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT_BIT
> # Loading work.glbl
> # ** Warning: (vsim-PLI-3003)
> C:/Xilinx/verilog/mti_se/unisims_ver/unisims_ver_SmartWrapper_source.v(18339):
> [TOFD] - System task or function '$lm_model' is not defined.
> #         Region:
> /test_clock/UUT/module1/GT_CUSTOM_INST/gt_1/gt_swift_1/I1
> # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
> # .main_pane.workspace
> # .main_pane.signals.interior.cs
> # No errors or warnings.
> # Break at test_clock.tfw line 82
> # Simulation Breakpoint: Break at test_clock.tfw line 82
> # MACRO ./test_clock.fdo PAUSED at line 17
>
> In this report I'm not andestend warning. All off signals from RocketIO
> module is x-state. But all of oter modules simulate succes.
> 
> :) And sorry my very bad english
Reply by ●August 23, 20062006-08-23
I am write Veriuser=3D $LMC_HOME/lib/pcnt.lib/swiftpli_mti.dll after line

; List of dynamically loaded objects for Verilog PLI applications in
fime modelsim.ini but this line deteted automatically.
Question : That line comment or not comment?



Jim Wu =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0):


> Have you checked AR  22214?
>
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=3Dyes&getPa=

gePath=3D22214

>
>
> HTH,
> Jim
> http://home.comcast.net/~jimwu88/tools/
>
> axalay@gmail.com wrote:
> > Modelsim report is:
> >
> > # Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl
> > # //  ModelSim SE 6.1b Sep  8 2005
> > # //
> > # //  Copyright Mentor Graphics Corporation 2005
> > # //              All Rights Reserved.
> > # //
> > # //  THIS WORK CONTAINS TRADE SECRET AND
> > # //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
> > # //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
> > # //  AND IS SUBJECT TO LICENSE TERMS.
> > # //
> > # do {test_clock.fdo}
> > # ** Warning: (vlib-34) Library already exists at "work".
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > # -- Compiling module stm4ser
> > #
> > # Top level modules:
> > # 	stm4ser
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > # -- Compiling module dcm1
> > #
> > # Top level modules:
> > # 	dcm1
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > # -- Compiling module clock
> > #
> > # Top level modules:
> > # 	clock
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > # -- Compiling module test_clock
> > #
> > # Top level modules:
> > # 	test_clock
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > # -- Compiling module glbl
> > #
> > # Top level modules:
> > # 	glbl
> > # vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps test_clock
> > glbl
> > # Loading work.test_clock
> > # Loading work.clock
> > # Loading work.dcm1
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.BUFG
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.IBUFG
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.DCM
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_divide_by_2
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_maximum_period_check
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_lost
> > # Loading work.stm4ser
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_CUSTOM
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT_BIT
> > # Loading work.glbl
> > # ** Warning: (vsim-PLI-3003)
> > C:/Xilinx/verilog/mti_se/unisims_ver/unisims_ver_SmartWrapper_source.v(=

18339):

> > [TOFD] - System task or function '$lm_model' is not defined.
> > #         Region:
> > /test_clock/UUT/module1/GT_CUSTOM_INST/gt_1/gt_swift_1/I1
> > # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
> > # .main_pane.workspace
> > # .main_pane.signals.interior.cs
> > # No errors or warnings.
> > # Break at test_clock.tfw line 82
> > # Simulation Breakpoint: Break at test_clock.tfw line 82
> > # MACRO ./test_clock.fdo PAUSED at line 17
> >
> > In this report I'm not andestend warning. All off signals from RocketIO
> > module is x-state. But all of oter modules simulate succes.
> >=20
> > :) And sorry my very bad english
Reply by ●August 23, 20062006-08-23
Thanks! When I write line Veriuser=3D
$LMC_HOME/lib/pcnt.lib/swiftpli_mti.dll  agayn end start simulate -
simulate succesful!. But when I start to compilyate library - this line
deleted agayn. Whay?


axalay@gmail.com =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0):


> I am write Veriuser=3D $LMC_HOME/lib/pcnt.lib/swiftpli_mti.dll after line
>
> ; List of dynamically loaded objects for Verilog PLI applications in
> fime modelsim.ini but this line deteted automatically.
> Question : That line comment or not comment?
>
>
>
> Jim Wu =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0):
>
> > Have you checked AR  22214?
> >
> > http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=3Dyes&get=

PagePath=3D22214

> >
> >
> > HTH,
> > Jim
> > http://home.comcast.net/~jimwu88/tools/
> >
> > axalay@gmail.com wrote:
> > > Modelsim report is:
> > >
> > > # Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl
> > > # //  ModelSim SE 6.1b Sep  8 2005
> > > # //
> > > # //  Copyright Mentor Graphics Corporation 2005
> > > # //              All Rights Reserved.
> > > # //
> > > # //  THIS WORK CONTAINS TRADE SECRET AND
> > > # //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
> > > # //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
> > > # //  AND IS SUBJECT TO LICENSE TERMS.
> > > # //
> > > # do {test_clock.fdo}
> > > # ** Warning: (vlib-34) Library already exists at "work".
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > > # -- Compiling module stm4ser
> > > #
> > > # Top level modules:
> > > # 	stm4ser
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > > # -- Compiling module dcm1
> > > #
> > > # Top level modules:
> > > # 	dcm1
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > > # -- Compiling module clock
> > > #
> > > # Top level modules:
> > > # 	clock
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > > # -- Compiling module test_clock
> > > #
> > > # Top level modules:
> > > # 	test_clock
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
> > > # -- Compiling module glbl
> > > #
> > > # Top level modules:
> > > # 	glbl
> > > # vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps test_clock
> > > glbl
> > > # Loading work.test_clock
> > > # Loading work.clock
> > > # Loading work.dcm1
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.BUFG
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.IBUFG
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.DCM
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_divide_by_2
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_maximum_period_che=

ck

> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_lost
> > > # Loading work.stm4ser
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_CUSTOM
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT_BIT
> > > # Loading work.glbl
> > > # ** Warning: (vsim-PLI-3003)
> > > C:/Xilinx/verilog/mti_se/unisims_ver/unisims_ver_SmartWrapper_source.=

v(18339):

> > > [TOFD] - System task or function '$lm_model' is not defined.
> > > #         Region:
> > > /test_clock/UUT/module1/GT_CUSTOM_INST/gt_1/gt_swift_1/I1
> > > # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
> > > # .main_pane.workspace
> > > # .main_pane.signals.interior.cs
> > > # No errors or warnings.
> > > # Break at test_clock.tfw line 82
> > > # Simulation Breakpoint: Break at test_clock.tfw line 82
> > > # MACRO ./test_clock.fdo PAUSED at line 17
> > >
> > > In this report I'm not andestend warning. All off signals from Rocket=

IO

> > > module is x-state. But all of oter modules simulate succes.
> > >=20
> > > :) And sorry my very bad english
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