Why No Process Shrink On Prior FPGA Devices ?

I'm wondering what intrinsic ecomomic, technical, or "other" barriers
have precluded FPGA device vendors from taking this step.   In other
words, why are there no advertised, periodic refreshes of older
generation FPGA devices.

In the microprocessor world, many vendors have established a long and
succesful history of developing a pin compatible product roadmap for
customers.  For the most part, these steps have allowed customers to
reap periodic technology updates without incurring the need to perform
major re-work on their printed circuit card designs or underlying
software.

On the Xilinx side of the fence there appears to be no such parallel.
Take for example, Virtex-II Pro.  This has been a proven work-horse for
many of our designs.    It takes quite a bit of time to truly
understand and harness all of the capabilities and features offered by
a platform device like this.      After making the investment to
develop IP and hardware targeted at this technology, is it unreasonable
to expect a forward looking roadmap that incorporates modest updates to
the silicon ?   A step that doesn't require a flow blown jump to a new
FPGA device family and subsequent re-work of the portfolio of hardware
and, very often, the related FPGA IP ?

Sure, devices like Virtex-5 offer capabilities that will be true
enablers for many customers (and for us at times as well).   But why
not apply a 90 or 65 nm process shrink to V2-Pro, provide modest speed
bumps to the MGT, along with minor refinements to the hardware
multipliers.  Maybe toss in a PLL for those looking to recover clocks
embedded in the MGT data stream etc.    And make the resulting devices
100% pin and code compatible with prior generations.

Perhaps I'm off in the weeds.  But, in our case, the ability to count
on continued refinement and update of a pin-comaptible products like
V2-Pro would result in more orders of Xilinx silicon as opposed to
fewer.

The absence of such refreshes in the FPGA world leads me to believe
that I must be naive.  So I am trying to understand where the logic is
failing.  Its just that there are times I wish the FPGA vendors could
more closely parallel what the folks in the DSP and micro-processor
world do ...

tweed_deluxe schrieb:

> I'm wondering what intrinsic ecomomic, technical, or "other" barriers
> have precluded FPGA device vendors from taking this step.   In other
> words, why are there no advertised, periodic refreshes of older
> generation FPGA devices.

it's just virtually impossible.

if you make a process schrink on some MCU for example after
the schrink the datasheet can remain almost the same with minor
changes.

now if we would technology shrink some FPGA family then the amount
of work to be done for new 'characterization' of the silicon is
enourmous.

and if you know the mask set pricing then you can easily understand
that this is not an option for any FPGA vendor.

some pincompat could be achived between families, maybe, but
if you want to have V2Pro in 'shrinked' technology (eg cheaper) then
it want happen. 

Antti
http://xilant.com

> now if we would technology shrink some FPGA family then the amount
> of work to be done for new 'characterization' of the silicon is
> enourmous.
>
> and if you know the mask set pricing then you can easily understand
> that this is not an option for any FPGA vendor.

So let me conclude this to make sure I understand:

1. You cannot shrink FPGAs because when you shrink them, you have to
update all the design PAR files to match the new timing. 2.
Characterizing the timing on these internal lines is a pain in the
butt. 3. Hence, nobody wants to invest that money when they could be
spending their time getting the timing right on their latest designs.

Sound right?

Let me throw some conservative numbers at this:
$ 10 million for the mask sets for a new family
$ 50 million in design, characterization, software upgrade,
manufacturing logistics
another $ 50 M in "lost opportunity cost", because we would have to
delay other work
Plus a much higher cost caused by the potential loss of the leadership
position that Xilinx enjoys in this industry.
Redesigning an old family would be an irresponsible waste of our
resources.
Peter Alfke

Brannon wrote:
> > now if we would technology shrink some FPGA family then the amount
> > of work to be done for new 'characterization' of the silicon is
> > enourmous.
> >
> > and if you know the mask set pricing then you can easily understand
> > that this is not an option for any FPGA vendor.
>
> So let me conclude this to make sure I understand:
>
> 1. You cannot shrink FPGAs because when you shrink them, you have to
> update all the design PAR files to match the new timing. 2.
> Characterizing the timing on these internal lines is a pain in the
> butt. 3. Hence, nobody wants to invest that money when they could be
> spending their time getting the timing right on their latest designs.
> 
> Sound right?

Brannon,

That, and more.

Back when going from 1u, to .8u, to .65u, etc. was as simple as just
making a mask where everything was smaller, shrinking was just good
business.  Cheaper parts, maybe even faster parts, same functionality.

But now, making something smaller is a complete re-design, with all
circuits getting completely re-simulated, and redone.  And finally the
layout has changed such that a plain shrink would violate all the design
rules.

Basically, not an option anymore.

The last shrink we did was 0.18u to 0.15u in Spartan 2E for cost reasons
(years ago).  It involved a lot of work, but just slightly less than a
completely new product, so it made sense.

Austin

Brannon wrote:
>> now if we would technology shrink some FPGA family then the amount
>> of work to be done for new 'characterization' of the silicon is
>> enourmous.
>>
>> and if you know the mask set pricing then you can easily understand
>> that this is not an option for any FPGA vendor.
> 
> So let me conclude this to make sure I understand:
> 
> 1. You cannot shrink FPGAs because when you shrink them, you have to
> update all the design PAR files to match the new timing. 2.
> Characterizing the timing on these internal lines is a pain in the
> butt. 3. Hence, nobody wants to invest that money when they could be
> spending their time getting the timing right on their latest designs.
> 
> Sound right?
> 

tweed_deluxe wrote:
> I'm wondering what intrinsic ecomomic, technical, or "other" barriers
> have precluded FPGA device vendors from taking this step.   In other
> words, why are there no advertised, periodic refreshes of older
> generation FPGA devices.

Reasonable question

> 
> In the microprocessor world, many vendors have established a long and
> succesful history of developing a pin compatible product roadmap for
> customers.  For the most part, these steps have allowed customers to
> reap periodic technology updates without incurring the need to perform
> major re-work on their printed circuit card designs or underlying
> software.
> 
> On the Xilinx side of the fence there appears to be no such parallel.
> Take for example, Virtex-II Pro.  This has been a proven work-horse for
> many of our designs.    It takes quite a bit of time to truly
> understand and harness all of the capabilities and features offered by
> a platform device like this.      After making the investment to
> develop IP and hardware targeted at this technology, is it unreasonable
> to expect a forward looking roadmap that incorporates modest updates to
> the silicon ?   A step that doesn't require a flow blown jump to a new
> FPGA device family and subsequent re-work of the portfolio of hardware
> and, very often, the related FPGA IP ?
> 
> Sure, devices like Virtex-5 offer capabilities that will be true
> enablers for many customers (and for us at times as well).   But why
> not apply a 90 or 65 nm process shrink to V2-Pro, provide modest speed
> bumps to the MGT, along with minor refinements to the hardware
> multipliers.  Maybe toss in a PLL for those looking to recover clocks
> embedded in the MGT data stream etc.    And make the resulting devices
> 100% pin and code compatible with prior generations.
> 
> Perhaps I'm off in the weeds.  But, in our case, the ability to count
> on continued refinement and update of a pin-comaptible products like
> V2-Pro would result in more orders of Xilinx silicon as opposed to
> fewer.
> 
> The absence of such refreshes in the FPGA world leads me to believe
> that I must be naive.  So I am trying to understand where the logic is
> failing.  Its just that there are times I wish the FPGA vendors could
> more closely parallel what the folks in the DSP and micro-processor
> world do ...

  The FPGA market is not growing all that quickly, so the funds are not
available for this.

  You will also find that the design life of FPGA products is shorter 
than DSP/microprocessors, plus they cannibalize sales of their 'hot new'
devices, as well as confuse the designers.

  Sometimes, there are physical barriers, like changes to flip chip, and 
whole-die bonding, that mandate BGA. There, backwards compatible has to
go - and that's the key reason for doing this.

  All those factors, mean this is unlikely to happen.

  What they CAN do, is try and keep ball-out compatible, over a couple 
of generations, but I'm not sure even that relatively simple effort is 
pushed too hard ?

-jg

They actually kinda do die shrinks, but they give the new die a new
name and alter a few other things.  Example, a Virtex 2 becomes a
Spartan 3, you get the idea...

For each step in the process technology they make the trade offs that
make sense for those geometries (e.g bigger memory).  They first
release a high priced wiz bang part with one name, then they follow up
with a lower price smaller die using the same process and give it a
different name.


tweed_deluxe wrote:
> I'm wondering what intrinsic ecomomic, technical, or "other" barriers
> have precluded FPGA device vendors from taking this step.   In other
> words, why are there no advertised, periodic refreshes of older
> generation FPGA devices.
>
> In the microprocessor world, many vendors have established a long and
> succesful history of developing a pin compatible product roadmap for
> customers.  For the most part, these steps have allowed customers to
> reap periodic technology updates without incurring the need to perform
> major re-work on their printed circuit card designs or underlying
> software.
>
> On the Xilinx side of the fence there appears to be no such parallel.
> Take for example, Virtex-II Pro.  This has been a proven work-horse for
> many of our designs.    It takes quite a bit of time to truly
> understand and harness all of the capabilities and features offered by
> a platform device like this.      After making the investment to
> develop IP and hardware targeted at this technology, is it unreasonable
> to expect a forward looking roadmap that incorporates modest updates to
> the silicon ?   A step that doesn't require a flow blown jump to a new
> FPGA device family and subsequent re-work of the portfolio of hardware
> and, very often, the related FPGA IP ?
>
> Sure, devices like Virtex-5 offer capabilities that will be true
> enablers for many customers (and for us at times as well).   But why
> not apply a 90 or 65 nm process shrink to V2-Pro, provide modest speed
> bumps to the MGT, along with minor refinements to the hardware
> multipliers.  Maybe toss in a PLL for those looking to recover clocks
> embedded in the MGT data stream etc.    And make the resulting devices
> 100% pin and code compatible with prior generations.
>
> Perhaps I'm off in the weeds.  But, in our case, the ability to count
> on continued refinement and update of a pin-comaptible products like
> V2-Pro would result in more orders of Xilinx silicon as opposed to
> fewer.
>
> The absence of such refreshes in the FPGA world leads me to believe
> that I must be naive.  So I am trying to understand where the logic is
> failing.  Its just that there are times I wish the FPGA vendors could
> more closely parallel what the folks in the DSP and micro-processor
> world do ...

No more die shrinks, since ant smaller process needs a different supply
voltage, and thus is an incompatible part.

Also Spartan may have been a version of Virtex in the past. Nowadays
the design goals are so much different ( die cost, speed, I/O vs logic
density, package cost) that the two product lines are diverging more
and more.
Remember the original Porsche? It was a VW with a modified body and
souped-up engine.
No more!
Peter Alfke

kayrock66@yahoo.com wrote:
> They actually kinda do die shrinks, but they give the new die a new
> name and alter a few other things.  Example, a Virtex 2 becomes a
> Spartan 3, you get the idea...
>
> For each step in the process technology they make the trade offs that
> make sense for those geometries (e.g bigger memory).  They first
> release a high priced wiz bang part with one name, then they follow up
> with a lower price smaller die using the same process and give it a
> different name.
> 
>

Thanks for the replies folks, I appreciate it.

These are answers I suspected but wanted to hear from the horses mouth.

I think the second paragraph of my post is the crux of what I was
getting at and Jim's comments are particularly germane.  Is the aspect
of maintaining pinout compatability across a few device generations a
poor business case as well ?  It would appear to be so ...

I understand the "Porsche" design philosophy and the apparant need to
remain on the bleeding edge (with the silicon) in order to create
and/or sustain a position of market leadership.   It's one particular
facet of a business model and, sometimes, it makes for wonderful
magazine advertisements.   For now, it seems that the company with the
biggest baddest FPGA is a pre-requisite for making the most money.
(Although placing and routing a fully loaded V4 LX200 on a Windows box
is an exercise in extreme patience :) )

>From a financial perspective, Toyota is more successful company than
Porsche.    I realize that these automobile analogies can be taken far
out of context.  But there are times when I can't help but desire a
little more "Toyota" and a little less "Porsche" from the big FPGA
outfits.

The rapid evolution of the silicon and underlying change in FPGA
feature sets does impose challenges (i.e. consequences).   The need to
significantly re-work existing hardware that seeks a modest tech
re-fresh is self evident .... and a rubbing point for ordinary average
joe's like me.

However, the stresses placed on the tool-chain developers cranking out
ISE, EDK, SysGen, and related IP must be formidable.  It probably also
makes things interesting for the FAE staff and support services.  The
latest "gee-whiz" device will (and does) pre-empt soreley needed
improvments to the design tools as well as refined integration and
interplay between them.  Integration that truly renders platform FPGA
design fluid, user friendly, bug-free, and productive.  I'm not saying
that Xilinx hasn't made key strides in merging the EDK, ISE, DSP, and
other flows.  It is the basis for many shining moments in our shop.
But, we've been users since day 1 and its got a long long way to go
before my co-workers and I go through a day without muttering a four
letter word :).

Maybe all of this banter is/was simply about wondering where to put the
eggs in the FPGA basket.  Asking if there is possibly more money to be
made by offering a "lesser device" or "more comprimised design
approach" that, increases the investment in other areas to yield
visibly superior tools, more FPGA IP, a quantum leap in productivity,
ease of upgrading to future silicon devices etc.


Regards,


Chris

This is a meaningful exchange of ideas.
But:
We have a "Toyota", it's called Spartan.
More seriously:
Mask shrinks, or redesigns to a maller geometry would definitely make
the chip smaller, probably  cheaper, but would achieve only a tiny
performance boost.
The days are long gone when the next technology made the chip
automatically much faster.
If we can eke a 10% speed improvement out of the process alone, we are
happy.
The real speed boost of 30+% comes mainly from more creative designs
and architectures, hard cores and better software. But not from smaller
feature sizes and thinner gate oxide.
(The trace-to-trace capacitance actually goes up with narrower traces
packed more closely together).
Higher performance requires radical innovation and real cleverness
these days.
Peter Alfke
=================
tweed_deluxe wrote:
> Thanks for the replies folks, I appreciate it.
>
> These are answers I suspected but wanted to hear from the horses mouth.
>
> I think the second paragraph of my post is the crux of what I was
> getting at and Jim's comments are particularly germane.  Is the aspect
> of maintaining pinout compatability across a few device generations a
> poor business case as well ?  It would appear to be so ...
>
> I understand the "Porsche" design philosophy and the apparant need to
> remain on the bleeding edge (with the silicon) in order to create
> and/or sustain a position of market leadership.   It's one particular
> facet of a business model and, sometimes, it makes for wonderful
> magazine advertisements.   For now, it seems that the company with the
> biggest baddest FPGA is a pre-requisite for making the most money.
> (Although placing and routing a fully loaded V4 LX200 on a Windows box
> is an exercise in extreme patience :) )
>
> >From a financial perspective, Toyota is more successful company than
> Porsche.    I realize that these automobile analogies can be taken far
> out of context.  But there are times when I can't help but desire a
> little more "Toyota" and a little less "Porsche" from the big FPGA
> outfits.
>
> The rapid evolution of the silicon and underlying change in FPGA
> feature sets does impose challenges (i.e. consequences).   The need to
> significantly re-work existing hardware that seeks a modest tech
> re-fresh is self evident .... and a rubbing point for ordinary average
> joe's like me.
>
> However, the stresses placed on the tool-chain developers cranking out
> ISE, EDK, SysGen, and related IP must be formidable.  It probably also
> makes things interesting for the FAE staff and support services.  The
> latest "gee-whiz" device will (and does) pre-empt soreley needed
> improvments to the design tools as well as refined integration and
> interplay between them.  Integration that truly renders platform FPGA
> design fluid, user friendly, bug-free, and productive.  I'm not saying
> that Xilinx hasn't made key strides in merging the EDK, ISE, DSP, and
> other flows.  It is the basis for many shining moments in our shop.
> But, we've been users since day 1 and its got a long long way to go
> before my co-workers and I go through a day without muttering a four
> letter word :).
>
> Maybe all of this banter is/was simply about wondering where to put the
> eggs in the FPGA basket.  Asking if there is possibly more money to be
> made by offering a "lesser device" or "more comprimised design
> approach" that, increases the investment in other areas to yield
> visibly superior tools, more FPGA IP, a quantum leap in productivity,
> ease of upgrading to future silicon devices etc.
> 
> 
> Regards,
> 
> 
> Chris