Why No Process Shrink On Prior FPGA Devices ?

Peter Alfke wrote:
> Higher performance requires radical innovation and real cleverness
> these days.
> Peter Alfke

Managing product costs do as well. Heavy re-engineering costs, new
regulatory certifications, multiply stocked SKUs for warranty
replacement, cross version updates because of component changes, and a
miriad of like problems make product life management a nightmare in the
fast moving FPGA world. Just parts cost reduction, combined with fewer
product rev costs, makes a whole lot of sense ... and the basic thrust
of the OP's arguments.

To sell Xilinx parts to and end user market, it's not just mask costs
that affect volume. The ripple changes down the customer chains are
many more real dollars than high mask costs .... just in regulatory
recertification, build and life management costs.

hi

fpga_toys@yahoo.com wrote:
> Peter Alfke wrote:
> > Higher performance requires radical innovation and real cleverness
> > these days.
> > Peter Alfke
>

pin compatability is just customer support, how about a 1 pin high
implies a self program from a small hardwired rom, which gets enough of
the chip off the ground, to work as a programmer for itself and others.
some of that extra space :-)

internally they don't have to be the same, just roughly the same, as
i'm sure there will be extra logic area.

or how about a single sided io series, with 2 edges of for for corners,
then a scale down is just more logic mapped to fewer pins. and extra
die copies per cut chip.

it just needs an interface mapping layer (ie new standard size pads, to
old shrunk size pads (hyper buffers? or Capacitive resource.).

and could someone put some analog low power fast comparators on
please??

cheers

jacko

http://indi.joox.net a 24 blue block CPU element (16 bit)

Peter Alfke (alfke@sbcglobal.net) wrote:

<snip>
: Higher performance requires radical innovation and real cleverness
: these days.
: Peter Alfke

Such as this?

http://www.tip.csiro.au/ISEC2003/talks/OWe2.pdf

JPL and Northrop Grumman built a 5k gate 8 bit CPU running at 20GHz by 
using superconducitng logic on a chip, it needs helium cycle cryogenics to 
hit 4.5k, but on the other hand it doesn't generate much heat being 
superconducting...

I'd have thought gate arrays would make an excelent tool for 
investigating the technology...

cds

jacko wrote:
>>
> pin compatability is just customer support, how about a 1 pin high
> implies a self program from a small hardwired rom, which gets enough of
> the chip off the ground, to work as a programmer for itself and others.
>
>
We have had that since the beginning, 20 years ago.
It is called "Master Mode Configuration"

Peter Alfke, Xilinx

Peter Alfke schrieb:

> jacko wrote:
> >>
> > pin compatability is just customer support, how about a 1 pin high
> > implies a self program from a small hardwired rom, which gets enough of
> > the chip off the ground, to work as a programmer for itself and others.
> >
> >
> We have had that since the beginning, 20 years ago.
> It is called "Master Mode Configuration"
>
> Peter Alfke, Xilinx

no - I think this is more like one of my past "idea for xilinx"

FPGA has built in hardware loader for __small__ rom. this rom contains
the logic to implement the actual loader, be it compact flash or nand
or
whatever. easily doable. just make a small part of the FPGA to become
alive first. allowing the rest of the FPGA to be configured from the
'bootstrap ipcore'.

nobody is doing it - but without that, the RAM nased FPGA configuration
solutions are still kinda PITA.

sure as Xilinx is now bringing back the parallel flash solutions from
XC2K
into S3E and Virtex-5 it becomes better, but the bootstrap idea would
still be the kicker!

Antti

Antti wrote:
> Peter Alfke schrieb:
>
> > jacko wrote:
> > >>
> > > pin compatability is just customer support, how about a 1 pin high
> > > implies a self program from a small hardwired rom, which gets enough of
> > > the chip off the ground, to work as a programmer for itself and others.
> > >
> > >
> > We have had that since the beginning, 20 years ago.
> > It is called "Master Mode Configuration"
> >
> > Peter Alfke, Xilinx
>
> no - I think this is more like one of my past "idea for xilinx"
>
> FPGA has built in hardware loader for __small__ rom. this rom contains
> the logic to implement the actual loader, be it compact flash or nand
> or
> whatever. easily doable. just make a small part of the FPGA to become
> alive first. allowing the rest of the FPGA to be configured from the
> 'bootstrap ipcore'.
>
> nobody is doing it - but without that, the RAM nased FPGA configuration
> solutions are still kinda PITA.
>
> sure as Xilinx is now bringing back the parallel flash solutions from
> XC2K
> into S3E and Virtex-5 it becomes better, but the bootstrap idea would
> still be the kicker!
>
> Antti


This is way off-topic, but I would like to expand on Antti's comment.

I'm planning on using my S3E sample pack board in this way. The FPGA
will be configured from the end of memory, while the software for the
embedded processor runs from the beginning of memory. The supplied
FLASH memory can easily handle both the configuration and the program.
The nice part of this configuration is that I don't need to waste
resources on a an internal BRAM based ROM in my design, and can use all
the BRAM's for RAM.

It would be nice, however; if the ability to boot from a NOR flash
could be expanded to NAND flash. Since many applications already
include a large NAND flash memory, this would allow you to use higher
density memories, while still dumping the separate configuration
memory. I realize that normal NAND flash is a bit more complex to
access, but there are now several vendors that supply NAND flash
memories that automatically make the first page readable in a
pseudo-microprocessor mode, and for the same reason - to allow a
processor to bootstrap from flash without a separate BIOS ROM.

Even if there was a requirement to use a NAND flash that auto-accessed
the first page, it  would be a nice improvement.

c d saunter wrote:
> Peter Alfke (alfke@sbcglobal.net) wrote:
>
> <snip>
> : Higher performance requires radical innovation and real cleverness
> : these days.
> : Peter Alfke
>
> Such as this?
>
> http://www.tip.csiro.au/ISEC2003/talks/OWe2.pdf
>
> JPL and Northrop Grumman built a 5k gate 8 bit CPU running at 20GHz by
> using superconducitng logic on a chip, it needs helium cycle cryogenics to
> hit 4.5k, but on the other hand it doesn't generate much heat being
> superconducting...
>
> I'd have thought gate arrays would make an excelent tool for
> investigating the technology...

>
> cds
Hi cds,
JPL and Northrop Grumman project is amasing. But you showed the slide
made in 2002. 4 years have passed, what is the latest advance? Do they
reach their goal? or don't get enough financial support and the project
was aborted?

Weng

Weng,

One thing that I think has been ignored by this thread, and yet is
probably the most important point, is that the semiconductor industry
has a roadmap.

That roadmap defines exactly what will happen, for as far into the
future as they are capable of either guessing, or hoping.  Which is
pretty far.

This is one of the reasons why the industry has been so successful:
there is no risk (really).  Everything from lithography, to wafers, to
chemicals, gases, reaction chambers, implanters, metals, packages, has
been set out for you.  There is a "goal" of what is needed, and you can
go and execute to that goal.  Yes, occasionally they ask for something
that can't be done (yet), like the Hi-K gate dielectric (unobtainium?).
 But generally, the fab industry and its ecosystem is a well "regulated"
technology monopoly.

If the technology is completely defined, then there is no way to build
anything that is not on the roadmap.  Doing so, is doomed to failure.

There are many examples of this, by the way.

First comes CMOS, then comes DRAM, and finally comes flash.  Even the
sequence of arrivals of the flavors of each technology node is
completely pre-ordained.

To even suggest that you would like to have a different thickness of a
single metal layer is completely heretical: it may happen once, but
since it isn't in the roadmap, it will not happen again.

Even those who own their own fabs are so constrained.  They must buy
their equipment from the same people that are supplying the "roadmap."
Thus even if you want to do something "out of the box" you are unable to
find the equipment to do it.  Our a "best known method."

As the dimensions crash into quantum mechanics limitations, it will be
interesting to see if the roadmap diverges, or if every "backroad" is
just as highly constrained as it is today.

My bet is that the roadmap will be with us for a long time, as it is a
proven method to nurture, supply, and execute, in semiconductors.

Austin

Austin Lesea wrote:
>...
> First comes CMOS, then comes DRAM, and finally comes flash.  Even the
> sequence of arrivals of the flavors of each technology node is
> completely pre-ordained.

Sounds like conspiracy theory :). I'd guess the driving force is the
market. Technology avenues are always opening up. Which ones
get pursued? Only the ones that have a good chance of getting
widely adopted. A technology or fab process that is only applicable
to one very specific problem...probably won't become mainstream.

Xilinx probably doesn't do its own fabrication, which means they
need to work within the system.

BTW what's next on the roadmap? What stocks should I invest in
now? :)

-Dave


-- 
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture

hi

i was thinking hardwired reset of device sets up via reset and set as a
i2c microprocessor, which serial loads from something like a 256Kbit
(or larger)
24AA256/24LC256/24FC256 EEPROM.

after the load, the circuit is clocked in to configure the fpga, and it
provides automatic on chip i2c interface. which along with a few fast
comparator inputs, and some RAM blocks, LUTS and a few mul blocks would
be a nice two chip solution for many applications.

having a manufacturer specific load up chip with resulting larger area
may not be good for an efficient bootstrap, and you loose the option to
have user code and data in the EEPROM, and a high level macro
specification of the logic interconnect.

having such a low cost standard boot would be a boon for fpga demand.

cheers.

p.s. don't forget the electron bolus on chip which extracts power
potential from inward spiral corriolis acceleration of high mobility
electrons in n-type spiral, using substrate zener effect for voltage
stabilization. (They work better when smaller)