ASMBL - hmmm

Been following the rollout of
Application Specific Modular BLock (ASMBL) at Xilinx.
Lots of gushing words, but what is it REALLY ?

Thus far we can glean :  Stripe layout, and areal bondpads
Not quite 'Revolutionary': Areal bondpads are nice to have,
and the Stripe layout has plus and minus columns :

Plus: Faster local speeds
Minus: Only to a certain ceiling
Plus: Faster Place/Route
Plus: Reduced routing cross points
Plus: Faster device Testing, & possible redundancy mapping
Plus: More consistant Place/Route migration
Minus: Tendancy to wastage : New IP -> New Column

CPLDs have been multiple-larger-block structured for years,
and Clock drivers on FPGAs are already have larger fabric
elements.

But more fun comes from what the analysts think all this means :

>"I believe we'll eventually see FPGAs that are fully application-specific,"
said Bryan Lewis, an analyst with Gartner Dataquest, San Jose. "But this is
a nice compromise without losing the economics of having an architecture
that can be used by multiple customers."

Er, isn't a 'fully application-specific FPGA' actually an ASIC ? :)

>"If Xilinx is doing a chip that is 90% perfect for the app, the price
difference would have to be strong justification to make the leap into an
ASIC," Snyder said.

Might be that the more defined stripes make the move to Structured ASICs
easier, and
this  'MASK FPGA'  segment would grow ?

Perhaps ASMBL means 'A Surfeit of Marketing BaLoney' ?

-jg

They make it sound like it is a response to structured ASICs but it sounds a
little like the QuickSliver stuff to me. QS is embedding custom blocks along
with FPGA like blocks. Also the Structured ASICs are biting the dust but QS
has hired 50% of all the top reconfigurable computing people I have a lot of
faith in their abilities.

Steve


"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:EbrBb.12264$ws.1161156@news02.tsnz.net...
> Been following the rollout of
> Application Specific Modular BLock (ASMBL) at Xilinx.
> Lots of gushing words, but what is it REALLY ?
>
> Thus far we can glean :  Stripe layout, and areal bondpads
> Not quite 'Revolutionary': Areal bondpads are nice to have,
> and the Stripe layout has plus and minus columns :
>
> Plus: Faster local speeds
> Minus: Only to a certain ceiling
> Plus: Faster Place/Route
> Plus: Reduced routing cross points
> Plus: Faster device Testing, & possible redundancy mapping
> Plus: More consistant Place/Route migration
> Minus: Tendancy to wastage : New IP -> New Column
>
> CPLDs have been multiple-larger-block structured for years,
> and Clock drivers on FPGAs are already have larger fabric
> elements.
>
> But more fun comes from what the analysts think all this means :
>
> >"I believe we'll eventually see FPGAs that are fully
application-specific,"
> said Bryan Lewis, an analyst with Gartner Dataquest, San Jose. "But this
is
> a nice compromise without losing the economics of having an architecture
> that can be used by multiple customers."
>
> Er, isn't a 'fully application-specific FPGA' actually an ASIC ? :)
>
> >"If Xilinx is doing a chip that is 90% perfect for the app, the price
> difference would have to be strong justification to make the leap into an
> ASIC," Snyder said.
>
> Might be that the more defined stripes make the move to Structured ASICs
> easier, and
> this  'MASK FPGA'  segment would grow ?
>
> Perhaps ASMBL means 'A Surfeit of Marketing BaLoney' ?
>
> -jg
>
>
>

Jim,

Now really, Jim, why so negative?  Isn't Xilinx justified in rolling out 
a new architecture with some fanfare?  Why is it that others are allowed 
to make outrageous and sometimes even false claims, and no one cares? 
Yet when we announce a truely revolutionary FPGA architecture, we get 
complaints?

If we can architect a device to allow for any collection of "stripes" 
and have the mask, and the software ready immediately, isn't that worth 
shouting about?

More and more we see market specific applications that require a more 
cost effective FPGA (eg software defined radio is a totally different 
mix of features than automotive entertainment center).  Why not be able 
to target a general purpose device to a specific market segment at 
reduced cost and better margins?  Might get more business that way, 
right?  If Spartan 3 is already cost effective against many ASICs, might 
this not make us even a better cost/benefit solution?

I do agree that the analysts do not have a clue, however.  For example, 
we are being compared to structured ASICs and other "hard" solutions. 
Those are misleading and false.  They are all dead-ends (just a re-spin 
of gate arrays with new clothing, or some other ASIC flow with window 
dressing liberally applied).

As for the details that I am sure you want to hear, you have to wait 
until the next press release.

Schedule:  architectual release, then specific family details, then 
product announcement.  Nothing new here.  Been following the same 
formula for many years.  Happy New Year!

Austin

Jim Granville wrote:
> Been following the rollout of
> Application Specific Modular BLock (ASMBL) at Xilinx.
> Lots of gushing words, but what is it REALLY ?
> 
> Thus far we can glean :  Stripe layout, and areal bondpads
> Not quite 'Revolutionary': Areal bondpads are nice to have,
> and the Stripe layout has plus and minus columns :
> 
> Plus: Faster local speeds
> Minus: Only to a certain ceiling
> Plus: Faster Place/Route
> Plus: Reduced routing cross points
> Plus: Faster device Testing, & possible redundancy mapping
> Plus: More consistant Place/Route migration
> Minus: Tendancy to wastage : New IP -> New Column
> 
> CPLDs have been multiple-larger-block structured for years,
> and Clock drivers on FPGAs are already have larger fabric
> elements.
> 
> But more fun comes from what the analysts think all this means :
> 
> 
>>"I believe we'll eventually see FPGAs that are fully application-specific,"
> 
> said Bryan Lewis, an analyst with Gartner Dataquest, San Jose. "But this is
> a nice compromise without losing the economics of having an architecture
> that can be used by multiple customers."
> 
> Er, isn't a 'fully application-specific FPGA' actually an ASIC ? :)
> 
> 
>>"If Xilinx is doing a chip that is 90% perfect for the app, the price
> 
> difference would have to be strong justification to make the leap into an
> ASIC," Snyder said.
> 
> Might be that the more defined stripes make the move to Structured ASICs
> easier, and
> this  'MASK FPGA'  segment would grow ?
> 
> Perhaps ASMBL means 'A Surfeit of Marketing BaLoney' ?
> 
> -jg
> 
> 
> 

"Austin Lesea"  wrote
> Jim,
>
> Now really, Jim, why so negative?

 I did not think I was negative on the engineering aspects ?
- I listed more pluses than minuses :) ?

> Isn't Xilinx justified in rolling out a new architecture with some
fanfare?

Of  course, but when the gush exceeds the hard data, expect some
analysts to get it wrong....

> Why is it that others are allowed
> to make outrageous and sometimes even false claims, and no one cares?
> Yet when we announce a truely revolutionary FPGA architecture, we get
> complaints?

"truely revolutionary" is a bold claim.

I can see good Engineering & Yield trade-offs in what's released so far, but
that's some way short of "truely revolutionary".

>
> If we can architect a device to allow for any collection of "stripes"
> and have the mask, and the software ready immediately, isn't that worth
> shouting about?

Can you clarify 'the mask' ?
Does this mean this will become like a block-hard-copy (but still FPGA),
where a large enough customer (/market?) can 'select the mix of stripes'
and a new die results ?
With real care, 'the mask' could even be effectively virtual by using
stripe based exposures at the wafer level.

Challenge there will be in the definition, to get devices to reach critical
mass, and
not go EOL as uptakes do not quite meet forecasts.

> More and more we see market specific applications that require a more
> cost effective FPGA (eg software defined radio is a totally different
> mix of features than automotive entertainment center).  Why not be able
> to target a general purpose device to a specific market segment at
> reduced cost and better margins?  Might get more business that way,
> right?  If Spartan 3 is already cost effective against many ASICs, might
> this not make us even a better cost/benefit solution?

So is this not a merchant market device, but an 'ASIC cherry pick' vehicle ?

-jg

Jim,
this was the first pre-announcement of something new from Xilinx. Don't
complain that it is vague, it is meant to be. It's supposed to create
interest, curiosity, perhaps even impatient excitement.
Exactly what the company wants. We cannot yet offer this for sale, but
we can create some expectations.
As Austin said, wait for the next, more detailed disclosure.
Any similarity with strip-tease is purely intentional...

Peter 
============================
Jim Granville wrote:
> 
> "Austin Lesea"  wrote
> > Jim,
> >
> > Now really, Jim, why so negative?
> 
>  I did not think I was negative on the engineering aspects ?
> - I listed more pluses than minuses :) ?
> 
> > Isn't Xilinx justified in rolling out a new architecture with some
> fanfare?
> 
> Of  course, but when the gush exceeds the hard data, expect some
> analysts to get it wrong....
> 
> > Why is it that others are allowed
> > to make outrageous and sometimes even false claims, and no one cares?
> > Yet when we announce a truely revolutionary FPGA architecture, we get
> > complaints?
> 
> "truely revolutionary" is a bold claim.
> 
> I can see good Engineering & Yield trade-offs in what's released so far, but
> that's some way short of "truely revolutionary".
> 
> >
> > If we can architect a device to allow for any collection of "stripes"
> > and have the mask, and the software ready immediately, isn't that worth
> > shouting about?
> 
> Can you clarify 'the mask' ?
> Does this mean this will become like a block-hard-copy (but still FPGA),
> where a large enough customer (/market?) can 'select the mix of stripes'
> and a new die results ?
> With real care, 'the mask' could even be effectively virtual by using
> stripe based exposures at the wafer level.
> 
> Challenge there will be in the definition, to get devices to reach critical
> mass, and
> not go EOL as uptakes do not quite meet forecasts.
> 
> > More and more we see market specific applications that require a more
> > cost effective FPGA (eg software defined radio is a totally different
> > mix of features than automotive entertainment center).  Why not be able
> > to target a general purpose device to a specific market segment at
> > reduced cost and better margins?  Might get more business that way,
> > right?  If Spartan 3 is already cost effective against many ASICs, might
> > this not make us even a better cost/benefit solution?
> 
> So is this not a merchant market device, but an 'ASIC cherry pick' vehicle ?
> 
> -jg

"Peter Alfke" wrote
> Jim,
> this was the first pre-announcement of something new from Xilinx. Don't
> complain that it is vague, it is meant to be. It's supposed to create
> interest, curiosity, perhaps even impatient excitement.
> Exactly what the company wants. We cannot yet offer this for sale, but
> we can create some expectations.
> As Austin said, wait for the next, more detailed disclosure.
> Any similarity with strip-tease is purely intentional...

Sounds like a new marketing manager fresh in from another industry.... ;-)

Even the technical press have taken the slightly misleading
 "Xilinx Unveils Revolutionary..."
and watered it down to the more accurate
"Xilinx set to debut novel FPGA architecture"
"..set to debut in a 90nm Virtex device in the first half of 2004, segments
function blocks into interchangeable columns, rather than squares on a
grid."

-jg

Jim,

It is NOT "hard-to-copy"!  Retains ALL of the reprogrammability and 
functionality of a 'true' FPGA -- just does it for a better cost/benefit 
trade-off.

"Hard-to-copy" means that if you make a mistake, you are toast.  It is 
inevitable that customers do not think of absolutely everything.  The 
new architecture will also allow us to provide EasyPath(tm), which if 
the customer calls up (which has happened, and boy are they glad they 
went with Xilinx!), and says "I forgot an inverter" we just modify the 
test program, and they are back in business IMMEDIATELY, with only a 
small charge (perhaps very small) for the modified test program work 
that we have to do.  No one else can do this, either!  In fact, 
EasyPath(tm) can be done for a few images (bistreams) and still retain 
the savings.  This fits it well with customers that wish to have single 
platforms that perform multiple functions (ie cellular basestations 
which are notorious for needing major changes every three months).

"Hard-to-copy" on a base station?  Disaster. End of the world.  Remember 
I worked in telecom for 23 years, and FPGAs saved by rear-end so many 
times, I can not count them all.  Ever had a Class-A recall of 100,000 
units from telephone companies?  Nightmare.  But if they are 
reprogrammable, we only needed a seed stock of 1,000 units, and then 
sent the new ones out, got back the old ones, reprogrammed them, and 
went on thru the whole 100K.  Saved the company.  Saved the product. 
Today you could send out a floppy, flash, or download it over the 'net.

That is why we state that "structured ASICs" are just a new description 
for a "buggy whip" -- not even in the same century as what we are doing.

As for 'revolution', who has ever announced such a chip architecture? 
Certainly no one in the FPGA industry.  Haven't ever heard of it 
anywhere else.

'Novel' is accurate as well.  It is new.  Prefer 'revolutionary', as 
that implies a complete re-thinking, and introduction of radically new 
benefits and features.  The press announcement mentioned 100 
innovations.  That is no small feat for a new device family.

I suppose Peter and I are guilty of working here, but some of the things 
that are coming up are awesome.......

Austin

Jim Granville wrote:
> "Peter Alfke" wrote
> 
>>Jim,
>>this was the first pre-announcement of something new from Xilinx. Don't
>>complain that it is vague, it is meant to be. It's supposed to create
>>interest, curiosity, perhaps even impatient excitement.
>>Exactly what the company wants. We cannot yet offer this for sale, but
>>we can create some expectations.
>>As Austin said, wait for the next, more detailed disclosure.
>>Any similarity with strip-tease is purely intentional...
> 
> 
> Sounds like a new marketing manager fresh in from another industry.... ;-)
> 
> Even the technical press have taken the slightly misleading
>  "Xilinx Unveils Revolutionary..."
> and watered it down to the more accurate
> "Xilinx set to debut novel FPGA architecture"
> "..set to debut in a 90nm Virtex device in the first half of 2004, segments
> function blocks into interchangeable columns, rather than squares on a
> grid."
> 
> -jg
> 
> 
> 
> 

Howdy Austin,

Austin Lesea wrote:
[...]
> "Hard-to-copy" means that if you make a mistake, you are toast.  It is 
> inevitable that customers do not think of absolutely everything.  The 
> new architecture will also allow us to provide EasyPath(tm), which if 
> the customer calls up (which has happened, and boy are they glad they 
> went with Xilinx!), and says "I forgot an inverter" we just modify the 
> test program, and they are back in business IMMEDIATELY, with only a 
> small charge (perhaps very small) for the modified test program work 
> that we have to do.  No one else can do this, either!  In fact, 
> EasyPath(tm) can be done for a few images (bistreams) and still retain 
> the savings.  This fits it well with customers that wish to have single 
> platforms that perform multiple functions (ie cellular basestations 
> which are notorious for needing major changes every three months).

Hmmmm.  If the customer is just changing the contents of a LUT, does 
that really require requal'ing EasyPath parts and changing the test 
program?  My understanding of EasyPath was that components and routes 
are tested, but I guess I don't have an exact definition of "component." 
  Could the contents of a LUT be changed without going through this 
hassle?  What about changing the polarity of a signal (or clk) going to 
a flop?  IOB parameters?  Contents of a BRAM?

[...]
> That is why we state that "structured ASICs" are just a new description 
> for a "buggy whip" -- not even in the same century as what we are doing.

And yet there are perfect applications for both buggy whips and 
structured ASICs.  Funny how an improvement on something doesn't 
necessarily out date everything before it, isn't it?

> As for 'revolution', who has ever announced such a chip architecture? 
> Certainly no one in the FPGA industry.  Haven't ever heard of it 
> anywhere else.
 >
 > 'Novel' is accurate as well.  It is new.  Prefer 'revolutionary', as
 > that implies a complete re-thinking, and introduction of radically new
 > benefits and features.  The press announcement mentioned 100
 > innovations.  That is no small feat for a new device family.

Where I work, whenever we hear the word "revolution," our ears perk up. 
  Because we know that that history has shown that most real revolutions 
fail, or at least, the first couple attempts at the revolution do.  Both 
old history and recent history, in all areas, from politics to the 
telecom world, to the semiconductor world.  It is VERY rare.  So if I 
were you, I'd personally shy away from that term unless it truly is 
revolutionary, in which case, as a shareholder, I hope you're not 
betting too much on it.

I am not saying I'm against revolutions when they are really called for. 
  I'm just saying that the word has been associated with A LOT of 
failure and that whenever I hear it coming from the mouth of a marketing 
droid, I hold onto my wallet.

> I suppose Peter and I are guilty of working here, but some of the things 
> that are coming up are awesome.......

Indeed they are.  It is a very exciting time for FPGAs, semiconductors, 
and electronics in general.  But just like we don't blame you for 
talking up Xilinx, don't blame us for trying to keep the marketers in 
check with all the fluff (and few details) they put out.

Have fun,

    Marc

Jim, here are some fictitious press releases that might be to your taste:

Boeing 747: like a 727, just bigger
Porsche 911: like a VW, just faster
Nokia cell phone: like a Walkie-Talkie, just lighter
Transistor: like a vacuum tube, just smaller
LCD display:  like a CRT, just flatter
FPGA: like a CPLD, just more complex

Any spectacular innovation can be de-dramatized.
Wouldn't excite any magazine editor, though.
Peter Alfke


Jim Granville wrote:
> 
> "Peter Alfke" wrote
> > Jim,
> > this was the first pre-announcement of something new from Xilinx. Don't
> > complain that it is vague, it is meant to be. It's supposed to create
> > interest, curiosity, perhaps even impatient excitement.
> > Exactly what the company wants. We cannot yet offer this for sale, but
> > we can create some expectations.
> > As Austin said, wait for the next, more detailed disclosure.
> > Any similarity with strip-tease is purely intentional...
> 
> Sounds like a new marketing manager fresh in from another industry.... ;-)
> 
> Even the technical press have taken the slightly misleading
>  "Xilinx Unveils Revolutionary..."
> and watered it down to the more accurate
> "Xilinx set to debut novel FPGA architecture"
> "..set to debut in a 90nm Virtex device in the first half of 2004, segments
> function blocks into interchangeable columns, rather than squares on a
> grid."
> 
> -jg

Marc,

--snip--

> 
> Hmmmm.  If the customer is just changing the contents of a LUT, does 
> that really require requal'ing EasyPath parts and changing the test 
> program?  My understanding of EasyPath was that components and routes 
> are tested, but I guess I don't have an exact definition of "component." 
>  Could the contents of a LUT be changed without going through this 
> hassle?  What about changing the polarity of a signal (or clk) going to 
> a flop?  IOB parameters?  Contents of a BRAM?

If they use a LUTRAM, SRL16, BRAM, then those features are 100% tested.

If they do not use a clock inversion, or do not use a different IO 
standard, then these are not tested.


> 
> [...]
> 
>> That is why we state that "structured ASICs" are just a new 
>> description for a "buggy whip" -- not even in the same century as what 
>> we are doing.
> 
> 
> And yet there are perfect applications for both buggy whips and 
> structured ASICs.  Funny how an improvement on something doesn't 
> necessarily out date everything before it, isn't it?

Oh yes.  I have a buggy whip at home.  Use it all of the time.  Right.

> 
>> As for 'revolution', who has ever announced such a chip architecture? 
>> Certainly no one in the FPGA industry.  Haven't ever heard of it 
>> anywhere else.
> 
>  >
>  > 'Novel' is accurate as well.  It is new.  Prefer 'revolutionary', as
>  > that implies a complete re-thinking, and introduction of radically new
>  > benefits and features.  The press announcement mentioned 100
>  > innovations.  That is no small feat for a new device family.
> 
> Where I work, whenever we hear the word "revolution," our ears perk up. 
>  Because we know that that history has shown that most real revolutions 
> fail, or at least, the first couple attempts at the revolution do.  Both 
> old history and recent history, in all areas, from politics to the 
> telecom world, to the semiconductor world.  It is VERY rare.  So if I 
> were you, I'd personally shy away from that term unless it truly is 
> revolutionary, in which case, as a shareholder, I hope you're not 
> betting too much on it.
> 
> I am not saying I'm against revolutions when they are really called for. 
>  I'm just saying that the word has been associated with A LOT of failure 
> and that whenever I hear it coming from the mouth of a marketing droid, 
> I hold onto my wallet.

Most revolutions fail?  Hmmm.  I suppose you also belong to the "glass 
is half empty crowd."

Austin