placing addiional caps across existing caps to reduce noise

To the subject at hand:  placing additional caps across existing caps 
does not reduce the noise (unless the dominant cause is lack of adequate 
capacitance).

The reason why the noise is bad is that the L (as in Ldi/dt) is most 
likely the largest, and most dominant factor, in the form of the via and 
traces to the bypass capacitor.

Many times people have placed additional caps on top of the the existing 
caps and wondered why the noise is not reduced:  well, you did not 
change the L in the equation, did you.  So why did you expect V to change?

You may have moved the resonant frequency (more often not), but often 
people make the mistake of assuming that a 0.1uF requires a 0.01uF and a 
0.001uF in parallel.  You can see that if the series L is dominant, you 
haven't even moved the frequency by more than a few percent by the small 
amount of additional capacitance.

Unfortunately, once the via and trace L is large, there is no way to 
make the noise less, withpout making a whole new pcb (re-layout).

More that once we have had to inform a customer that there is "no hope" 
for their pcb because the series L in their layout is dominant, and 
there is no way to reduce it.

And, we have then helped them re-layout their pcb and making their 
system work just fine (as, if you know what you are doing, this is not a 
hard problem to solve).

Mark Alexander's power distribution application note represents the 
latest state of our power distribution sysem "knowledge."

As we learn more, we will certainly update the applications note.

Again, my apologies to the group for a new thread, on an old subject.

Austin

Austin Lesea wrote:
> Unfortunately, once the via and trace L is large, there is no way to
> make the noise less, withpout making a whole new pcb (re-layout).
>
> More that once we have had to inform a customer that there is "no hope"
> for their pcb because the series L in their layout is dominant, and
> there is no way to reduce it.

This is certainly true, and been the cause for more than a few
re-layouts.

At the same time, the chip carrier PCB in most BGA packages also has
via's (probably a lot smaller) which add to the series L which are
beyound your control, so you only have half, or less of the series L
variable in your control. This is even more difficult with older BG
series parts where there are also bonding wires in the equation.

The only reason for stacking a mix of caps in checkout, is just to
verify that it's not a bulk capacitance problem.

It would be nice if Xilinx specified both the R and L for these chip
carrier PCB's vias/traces, along with chip carrier interplance
capacitance, and current profiles to better model both power system
performance, and I/O performance. Or at least gave firm numbers on what
the user PCB values can be, before the combine result would be unstable
by design.

Austin Lesea wrote:
> To the subject at hand:  placing additional caps across existing caps
> does not reduce the noise (unless the dominant cause is lack of adequate
> capacitance).
>
> The reason why the noise is bad is that the L (as in Ldi/dt) is most
> likely the largest, and most dominant factor, in the form of the via and
> traces to the bypass capacitor.
>
> Many times people have placed additional caps on top of the the existing
> caps and wondered why the noise is not reduced:  well, you did not
> change the L in the equation, did you.  So why did you expect V to change?
>
> You may have moved the resonant frequency (more often not), but often
> people make the mistake of assuming that a 0.1uF requires a 0.01uF and a
> 0.001uF in parallel.  You can see that if the series L is dominant, you
> haven't even moved the frequency by more than a few percent by the small
> amount of additional capacitance.

What do you think about the idea that if the caps are connected
directly to good low impedance power planes that the location of the
caps are not critical at all.  I have been discussing this in
comp.arch.embedded and have not gotten much negative feedback except
some claim that more is always better and that multiple values are not
needed.

A recent SI/EMI class I took says that you can put a relatively small
number of caps pretty much anywhere on the board as long as they are
coupled to the power planes with no traces, just the via.  This gives a
very low impedance connection to the planes and the planes give a very
low impedance connection to the chip.  It was also shown that to get a
low impedance over a broad bandwidth multiple values are needed to push
the impedance down and the parallel resonance up.  High loss capacitors
(X7R/X5R vs. C0G) were also recommended to reduce the signficance of
the parallel resonance.

Does any of this sound correct to you?  It was sure convincing in the
class and appears to be a very sure way of getting low noise on the
power planes and thereby on the chip power pins!

rickman wrote:
> What do you think about the idea that if the caps are connected
> directly to good low impedance power planes that the location of the
> caps are not critical at all.  I have been discussing this in
> comp.arch.embedded and have not gotten much negative feedback except
> some claim that more is always better and that multiple values are not
> needed.

On proto boards I'm always worried about process controls, and
frequently avoid flying probe testing since it only tests a small
number of the connections anyway. One of the concerns has always been
plating managment, so where I can on proto (and most production boards)
I still place the caps across the pwr/gnd vias when I can, simply to
take the via/plane plating reliability out of the question. Stacking
caps on problem boards, is just a second check, as high frequency caps
are the only thing at the pads normally, so a little bulk stacked on it
just takes the via plating out of the question a bit.

On production boards, the vendors will generall work with you to
optimize plating density across the board, so it's much less of a
problem.

fpga_toys@yahoo.com wrote:
> rickman wrote:
> > What do you think about the idea that if the caps are connected
> > directly to good low impedance power planes that the location of the
> > caps are not critical at all.  I have been discussing this in
> > comp.arch.embedded and have not gotten much negative feedback except
> > some claim that more is always better and that multiple values are not
> > needed.
>
> On proto boards I'm always worried about process controls, and
> frequently avoid flying probe testing since it only tests a small
> number of the connections anyway. One of the concerns has always been
> plating managment, so where I can on proto (and most production boards)
> I still place the caps across the pwr/gnd vias when I can, simply to
> take the via/plane plating reliability out of the question. Stacking
> caps on problem boards, is just a second check, as high frequency caps
> are the only thing at the pads normally, so a little bulk stacked on it
> just takes the via plating out of the question a bit.
>
> On production boards, the vendors will generall work with you to
> optimize plating density across the board, so it's much less of a
> problem.

If you have problems with via plating, don't you have much bigger
problems to worry about than cap placement?

rickman wrote:
> If you have problems with via plating, don't you have much bigger
> problems to worry about than cap placement?

On production boards, it's simply not acceptable.

On proto boards, it's only a problem for high current vias (pwr/gnd),
which is largely avoided if that's where the caps are too, since it
averages out the current spikes and reduces any voltage drop across the
bad plate. Even then, the few places that it was a problem at all,
where the small BGA vias ... everything else is large enough you never
see it.

rickman wrote:
> If you have problems with via plating, don't you have much bigger
> problems to worry about than cap placement?

I suppose you can always break out the micro/milli ohm meter and double
check every power ground via to plane .... but it's just easier to add
bulk caps as a check for problem boards, since the BGA is already
mounted anyway, and no way to reliably ohm it.

Austin Lesea <austin@xilinx.com> wrote:


> To the subject at hand:  placing additional caps across existing caps 
> does not reduce the noise (unless the dominant cause is lack of adequate 
> capacitance).

> The reason why the noise is bad is that the L (as in Ldi/dt) is most 
...

On that subject:
The webpages for Spartan 5 talk about "Virtex-5 sparse chevron packaging
effectively positions bypass capacitors on-substrate"

I didn't find any further information about these capacitors.
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Uwe Bonnes schrieb:

> Austin Lesea <austin@xilinx.com> wrote:
>
>
> > To the subject at hand:  placing additional caps across existing caps
> > does not reduce the noise (unless the dominant cause is lack of adequate
> > capacitance).
>
> > The reason why the noise is bad is that the L (as in Ldi/dt) is most
> ...
>
> On that subject:
> The webpages for Spartan 5 talk about "Virtex-5 sparse chevron packaging
> effectively positions bypass capacitors on-substrate"
>
> I didn't find any further information about these capacitors.
> --
> Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Spartan-5 ? is Spartan-4 going to be skipped?

Antti

Antti <Antti.Lukats@xilant.com> wrote:

> Spartan-5 ? is Spartan-4 going to be skipped?

Ouch!

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------