bidirectional connection between two bidirectional ports

"Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message 
news:44fd3402$0$11094$3b214f66@tunews.univie.ac.at...
>I changed my design to (like Antti suggested):
>  port1 <= port2 when (port1_output_enable = '1') else 'Z';
>  port2 <= port1 when (port2_output_enable = '1') else 'Z';
> but this doesn't work in Altera Quartus Simulation :-(((
> the output at port1 and port2 shows "Z" when enabled and otherwise 
> "Unknown"
> Is this just an malfunction of Quartus Simulation???? and will it work in 
> real hardware (Altera MAX3000A)???

Depends completely on what your model for port1 and port2 are doing.  Do you 
have some form of VHDL model for the external 'things' that are driving 
port1 and port2?  Are you trying to 'force' them?  If forcing, how?

Since port1 and port2 are I/O pins on your design, then when things are just 
'sitting there' (i.e. port1_output_enable and port2_output_enable are both 
'0') then port1 and port2 will be sitting there at 'Z'.  When 
port1_output_enable goes to a '1', your design should start driving port1 
(i.e. now it's an output) with whatever is on port2 (which is now an input). 
So, ask yourself, at that time, what is driving port2?  The answer is that 
it is your simulation testbench, port2 needs to be driven, at that time, 
just like any other input to your design.  Once you've got that understood, 
you'll need to answer the same questions about port1 when your signal 
'port2_output_enable' is active.

KJ 

Tanks for your answers ...
Now it works - it was just a handling error of the Quartus Simulator by me 
(embarrassing)
Manfred


"KJ" <kkjennings@sbcglobal.net> schrieb im Newsbeitrag 
news:O6cLg.15443$%j7.3213@newssvr29.news.prodigy.net...
>
> "Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message 
> news:44fd3402$0$11094$3b214f66@tunews.univie.ac.at...
>>I changed my design to (like Antti suggested):
>>  port1 <= port2 when (port1_output_enable = '1') else 'Z';
>>  port2 <= port1 when (port2_output_enable = '1') else 'Z';
>> but this doesn't work in Altera Quartus Simulation :-(((
>> the output at port1 and port2 shows "Z" when enabled and otherwise 
>> "Unknown"
>> Is this just an malfunction of Quartus Simulation???? and will it work in 
>> real hardware (Altera MAX3000A)???
>
> Depends completely on what your model for port1 and port2 are doing.  Do 
> you have some form of VHDL model for the external 'things' that are 
> driving port1 and port2?  Are you trying to 'force' them?  If forcing, 
> how?
>
> Since port1 and port2 are I/O pins on your design, then when things are 
> just 'sitting there' (i.e. port1_output_enable and port2_output_enable are 
> both '0') then port1 and port2 will be sitting there at 'Z'.  When 
> port1_output_enable goes to a '1', your design should start driving port1 
> (i.e. now it's an output) with whatever is on port2 (which is now an 
> input). So, ask yourself, at that time, what is driving port2?  The answer 
> is that it is your simulation testbench, port2 needs to be driven, at that 
> time, just like any other input to your design.  Once you've got that 
> understood, you'll need to answer the same questions about port1 when your 
> signal 'port2_output_enable' is active.
>
> KJ
> 

Manfred Balik wrote:
> Hello,
> I am using an Altera MAX3000A CPLD to make level conversion from 5V-TTL to
> 3.3V-TTL (and further jobs...).
> My problem is - I can't connect two bidirectional ports directly to get a
> bidirectional connection.
> I'm using Altera Quartus II, a direct connection produces an error message
> and a simple VHDL-block doesn't solve the problem, too.
> my VHDL-code is like:
> ENTITY ...
> port1 : INOUT STD_LOGIC;
> port2 : INOUT STD_LOGIC;
> ARCHITECTURE...
> port1 <= port2;
> port2 <= port1;
>
> How can I make a bidirectional connection between two bidirectional ports???
> thanks, Manfred

Take a look at Analog Devices line of level translators -
http://www.analog.com/en/subCat/0,2879,767%255F828%255F0%255F%255F0%255F,00.html
The ADG3301/04/08 will connect 1/4/8-bit bidirectional buses together
with 3-state control.

Marc