How to resolve a Xilinx 8.1 BlockRAM problem

Hi,
I need your help.

My project uses BlockRAM by Xilinx.

I used CoreGenerator 6.2 to generate BlockRAM bram64_8,
and Xilinx free 8.1 ISE version.

By using code generated for ModelSim simulation, it works well
without any error.

But while compiling with Xilinx 8.1 ISE, it generates the
following errors:

ERROR:NgdBuild:604 - logical block
 'MG_x_A3/bram64_8_A/BU5' with type 'RAMB16' could not
 be resolved. A pin name misspelling can cause this,
 a missing edif or ngc file, or the misspelling of a type name.
 Symbol 'RAMB16' is not supported in target 'virtex2'.

I couldn't find any 'RAMB16' in my vhdl files.

What is wrong? How to correct it?

Thank you.

Weng

Weng Tianxiang wrote:
> Hi,
> I need your help.
> 
> My project uses BlockRAM by Xilinx.
> 
> I used CoreGenerator 6.2 to generate BlockRAM bram64_8,
> and Xilinx free 8.1 ISE version.
> 
> By using code generated for ModelSim simulation, it works well
> without any error.
> 
> But while compiling with Xilinx 8.1 ISE, it generates the
> following errors:
> 
> ERROR:NgdBuild:604 - logical block
>  'MG_x_A3/bram64_8_A/BU5' with type 'RAMB16' could not
>  be resolved. A pin name misspelling can cause this,
>  a missing edif or ngc file, or the misspelling of a type name.
>  Symbol 'RAMB16' is not supported in target 'virtex2'.
> 
> I couldn't find any 'RAMB16' in my vhdl files.
> 
> What is wrong? How to correct it?
> 
> Thank you.
> 
> Weng

Do you have your library specified?  I'm not a VHDL guy but I know the 
libraries are needed, in this case the unisim library in particular. 
The following is the first few lines from the control.vhd sample file 
for the Spartan3E Starter Kit:
_____________________________________________________________________

--
-- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by 
control.psm
-- and assmbled using KCPSM2 or KCPSM3 assembler.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also 
used during
-- simulation. The source can be viewed at 
%XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--

John_H wrote:
> Weng Tianxiang wrote:
> > Hi,
> > I need your help.
> >
> > My project uses BlockRAM by Xilinx.
> >
> > I used CoreGenerator 6.2 to generate BlockRAM bram64_8,
> > and Xilinx free 8.1 ISE version.
> >
> > By using code generated for ModelSim simulation, it works well
> > without any error.
> >
> > But while compiling with Xilinx 8.1 ISE, it generates the
> > following errors:
> >
> > ERROR:NgdBuild:604 - logical block
> >  'MG_x_A3/bram64_8_A/BU5' with type 'RAMB16' could not
> >  be resolved. A pin name misspelling can cause this,
> >  a missing edif or ngc file, or the misspelling of a type name.
> >  Symbol 'RAMB16' is not supported in target 'virtex2'.
> >
> > I couldn't find any 'RAMB16' in my vhdl files.
> >
> > What is wrong? How to correct it?
> >
> > Thank you.
> >
> > Weng
>
> Do you have your library specified?  I'm not a VHDL guy but I know the
> libraries are needed, in this case the unisim library in particular.
> The following is the first few lines from the control.vhd sample file
> for the Spartan3E Starter Kit:
> _____________________________________________________________________
>
> --
> -- Definition of a dual port ROM for KCPSM2 or KCPSM3 program defined by
> control.psm
> -- and assmbled using KCPSM2 or KCPSM3 assembler.
> --
> -- Standard IEEE libraries
> --
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> --
> -- The Unisim Library is used to define Xilinx primitives. It is also
> used during
> -- simulation. The source can be viewed at
> %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
> --
> library unisim;
> use unisim.vcomponents.all;
> --
> --

Hi,
Yes, I used it as following statements show:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.MG_x_Constant.all;
LIBRARY unisim;
USE UNISIM.VCOMPONENTS.ALL;

The library is specified in the project and all modules are compiled
with errors:
WARNING:NgdBuild:486 - Attribute "INITP_07" is not allowed on symbol
"BU8" of
   type "RAMB16".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "SRVAL_A" is not allowed on symbol
"BU8" of
   type "RAMB16".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "SRVAL_B" is not allowed on symbol
"BU8" of
   type "RAMB16".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "WRITE_MODE_A" is not allowed on
symbol "BU8"
   of type "RAMB16".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "WRITE_MODE_B" is not allowed on
symbol "BU8"
   of type "RAMB16".  This attribute will be ignored.
ERROR:NgdBuild:604 - logical block
   'MG_x_A4/BlockRAM64_16_2_32k_00/bram64_16_A/BU8' with type 'RAMB16'
could not
   be resolved. A pin name misspelling can cause this, a missing edif
or ngc
   file, or the misspelling of a type name. Symbol 'RAMB16' is not
supported in
   target 'virtex2'.

I never used any signals appeared in the above warning and errors.

What I am doing now is download latest 8.2 ISE and re-generate all
Block RAM modules again and see if the above errors happens again.

Thank you.

Weng

Weng Tianxiang schrieb:

> ERROR:NgdBuild:604 - logical block
>  'MG_x_A3/bram64_8_A/BU5' with type 'RAMB16' could not
>  be resolved. A pin name misspelling can cause this,
>  a missing edif or ngc file, or the misspelling of a type name.
>  Symbol 'RAMB16' is not supported in target 'virtex2'.
> 
> I couldn't find any 'RAMB16' in my vhdl files.

No, not in your VHDL.
But the RAM block that you generated uses it internally.

You will not get any VHDL code for the internals of the generated core.
Just a netlist (edif or ngc) and a simulation model.

Kolja Sulimma

Kolja Sulimma wrote:
> Weng Tianxiang schrieb:
>
> > ERROR:NgdBuild:604 - logical block
> >  'MG_x_A3/bram64_8_A/BU5' with type 'RAMB16' could not
> >  be resolved. A pin name misspelling can cause this,
> >  a missing edif or ngc file, or the misspelling of a type name.
> >  Symbol 'RAMB16' is not supported in target 'virtex2'.
> >
> > I couldn't find any 'RAMB16' in my vhdl files.
>
> No, not in your VHDL.
> But the RAM block that you generated uses it internally.
>
> You will not get any VHDL code for the internals of the generated core.
> Just a netlist (edif or ngc) and a simulation model.
>
> Kolja Sulimma

Hi Kolja,
Thank you very much for your help.

The problem seems resolved.
Now it is compiling and everything works well.

The free download WebPack is at fault.

What I have done to correct the errors are as follows:
1. Re-download the latest WebPack version with their service pack;
2. Re-generate all Block RAM modules;
3. It fails with Virtex 2 chips;
4. It suceeds with Virtex 4 chips, what I have used is: 4vlx25sf363-12.
The block RAM generated code can be used with the above chip.

That is all I have done.

If it had been a paid version of Xilinx ISE, the above errors would
have never happend before.

Thank you.

Weng