Exploring Quartus' Messages and Warnings

During the synthesis process, Quartus reports "Ignoring invalid
Fast-IO-Timing Assignments" which I am not able to discover, since
Quartus does not say WHERE or WHICH assignment is set incorrectly. Any
Idea ?

alterauser wrote:
> During the synthesis process, Quartus reports "Ignoring invalid
> Fast-IO-Timing Assignments" which I am not able to discover, since
> Quartus does not say WHERE or WHICH assignment is set incorrectly. Any
> Idea ?

Did you try
- Double clicking on the message?
- Right click to pull up a menu that says 'Locate in..."?

Usually one of those two methods locates the source of the error.
Don't recall if it works for the particular error message that you've
posted though

KJ

I think there is also a section "ignored timing assignments" in the 
timing-report.

Thomas

www.entner-electronics.com

"alterauser" <fpgaengineerfrankfurt@arcor.de> schrieb im Newsbeitrag 
news:1157471016.274755.295470@d34g2000cwd.googlegroups.com...
> During the synthesis process, Quartus reports "Ignoring invalid
> Fast-IO-Timing Assignments" which I am not able to discover, since
> Quartus does not say WHERE or WHICH assignment is set incorrectly. Any
> Idea ?
> 

@both:

Right-clicking and trying to locate it, brought no result, however. :-(

I know about the section "ignored timing reqs". - was empty in this
case.

alterauser wrote:
> During the synthesis process, Quartus reports "Ignoring invalid
> Fast-IO-Timing Assignments" which I am not able to discover, since
> Quartus does not say WHERE or WHICH assignment is set incorrectly. Any
> Idea ?

I would start a new project with a clean
working directory and default assignments
except for the file list.

Do:

 Processing, Start, Analysis + Synthesis


Once that works start adding other
assignments one at a time.




                 -- Mike Treseler

Hi Mike, yes of course I did that (in fact I partly disabled one
contraints after another) - but I think it should be more convenient to
be pointed directly to an errar, rather than doing research on this,
since the next error like this will appear shortly most likely...

alterauser wrote:
> Hi Mike, yes of course I did that (in fact I partly disabled one
> constraints after another)

So, what did you find?
Where was the error coming from?

> - but I think it should be more convenient to
> be pointed directly to an errar, rather than doing research on this,
> since the next error like this will appear shortly most likely...

If you can't find a workaround, call the "man"
http://www.altera.com/support/spt-index.html


        -- Mike Treseler

Are you sure that when you look at the assignments, in the assignament 
editor, that you don't have Fast Output/Input Enable Register enabled 
anywhere?

Description of Fast Output:
Implements an output enable register in a cell that has a fast, direct 
connection to an I/O pin. If such a fast, direct connection to the I/O pin 
is not available in the I/O cell hardware, this option instructs the Fitter 
to lock the output enable register in the LAB adjacent to the I/O cell it is 
feeding.Turning on the Fast Output Enable Register option can help maximize 
I/O timing performance, for example, by permitting fast clock-to-output 
times. Turning this option off for a particular signal prevents the Fitter 
from implementing the signal automatically in an I/O cell or locking down 
the output enable register in the LAB adjacent to the I/O cell. This option 
is ignored if it is applied to anything other than a register or an output 
or bidirectional pin fed by a register.







"alterauser" <fpgaengineerfrankfurt@arcor.de> wrote in message 
news:1157471016.274755.295470@d34g2000cwd.googlegroups.com...
> During the synthesis process, Quartus reports "Ignoring invalid
> Fast-IO-Timing Assignments" which I am not able to discover, since
> Quartus does not say WHERE or WHICH assignment is set incorrectly. Any
> Idea ?
> 

Hello

I know what the e.g. "Fast IO" options do to the design and I have
several of them constraining my ADC/DAC driving clocks as well as the
input cells aquiring data from the ADCs and so on..

In the particlar case, it was a fast option of a DDR-cell.

But the question ist not how to find an error in THIS design, but how
one can quickly locate an error in general.

As said, I found the misassignment by partly clicking on and off the
options one ather the other, but this is not a fine way. Quartus should
report this like "Assignment No 8 invalid", since the assignment ARE
numbered. 

Just an Idea ...

Typically the Ignored Timing Assignments in the Timing Analysis report
section will give you  details as to which signals are generating the
warning.  You can also right click on a signal within this report and
choose Locate / Locate In Assignment Editor.  I've never had any
difficulty finding a signal that had a timing parameter which Quartus
was ignoring.


alterauser wrote:
> Hello
>
> I know what the e.g. "Fast IO" options do to the design and I have
> several of them constraining my ADC/DAC driving clocks as well as the
> input cells aquiring data from the ADCs and so on..
>
> In the particlar case, it was a fast option of a DDR-cell.
>
> But the question ist not how to find an error in THIS design, but how
> one can quickly locate an error in general.
>
> As said, I found the misassignment by partly clicking on and off the
> options one ather the other, but this is not a fine way. Quartus should
> report this like "Assignment No 8 invalid", since the assignment ARE
> numbered. 
> 
> Just an Idea ...