Anyone who have succeeded with BPI configuration on the Spartan-3E Starter Kit

Hi!

I've tried to explore the BPI (Byte Peripheral Interface) configuration
mode on the Spartan-3E starter kit without success.

I've followed the "EDK Flashwriter.ppt" I got from Xilinx and I've
managed to burn uClinux images and bin-files anywhere I want in the
StrataFlash, but my Spartan-3E Starter boards (rev c) never configure
themselves from the Intel StrataFlash device:

- I have strapped MODE(2:0) to "010" (BPI/UP) as well as "011"
(BPI/DOWN).
- I have stored my BIN-files generated from my bit-files with the
"promgen -p bin -c FF -o output.bin -u 0x0 input.bit" and "promgen -p
bin -c FF -o output.bin -d 0xFFFFF input.bit" commands at offset 0x2000
(BPI/UP) as well as offset 0xFBAA9F (BPI/DOWN) in the StrataFlash.
- When I configure the FPGA with bit-files via JTAG the MicroBlaze
starts executing the bootloader application from internal BRAM, moving
the uClinux image from the StrataFlash to the DDR SDRAM and then starts
to execute from there, but this never succeeds with my design stored in
StrataFlash.

There is a small CPLD (XC2C64) on the board connected to XC-A(23:20),
XC-DONE, etc.
I believe this device has to drive A(24:20) high or low during FPGA
configuration in order to have the FPGA fetch the bitstream from the
top/bottom of the StrataFlash. I don't have access to sourcecode for
this CPLD, but obviously have relied on it to do it's job. I guess that
the question is if it does so on a std revC Spartan-3E Starter board?

I've read the S3E/StrataFlash article
(http://www.xilinx.com/publications/xcellonline/xcell_54/xc_pdf/xc_strata54.pdf)
and compared to the Spartan-3E Starter schematics:
It appears as if the S3E-kit has too weak pulldown (4.7 kohm instead of
340 ohm) on the LDC2 signal so that the StrataFlash might not have time
to swap between *16 mode to *8 mode (takes up to 1000 ns) before the
S3E starts to fetch data from it. However both workaround #2 and #3
ought to make sure that the FPGA configures once it finds the right
"initialization sequence".

Regarding the configrate setting I haven't changed it since I believe
that the default configrate=6 => 1,5 MHz should be ok with the 110 -
150 ns accesstime of the StrataFlash.

I guess that offset 0x2000 and 0xFBAA9F applies for XC3S500E devices.
What offset values applies for XC3S1200E and XC3S1600E devices ..... or
can I use almost any offset in the StrataFlash since an S3E-device in
BPI-mode will search the StrataFlash until it finds the right
"initialization sequence" and then successfully configure from there?


The board:
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US

I'm using EDK8.2i (SP1) and ISE8.2i (SP2) and Rev C boards.

Please help.

Hello,

The sourcecode of the CPLD... <http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm>