Help for Altera Nios II Cyclone EP1C12 evaluation kit!

Hello out there!

   I have purchased an Altera Nios II Cyclone based (EP1C12F324) evalution 
kit a while ago and didn't get to work with until recently.  At first I was 
happy to see how quickly I got the board up and running and interacting with 
my PC through an Ethernet LAN and serving web pages using the uClinux 
on-board http server.

   Having had enough of the demo I started developping an application of my 
own.  I first downloaded (via the USB cable connector that provides a USB 
Blaster interface) a very simple code file to start flashing the LEDs.  When 
that didn't work, I simplified the code to an even simpler test case where 
only one LED was involved.  After that not even working, I started combing 
through the documentation in search for some clues.  This is when I noticed 
a lot of little discrepencies between the real board and the document set.

    To this day, I still haven't been able to get a simple LED to flash (not 
even once).  I am getting a bit impatient with the whole thing and might 
just go back to a Xilinx board that is sitting around my ofice.  Before I do 
that, I would like to know if any one out there has played with this board 
and might have some hints for me.

    Thanks in advance for any tid bits.

P.S.  When I download the code to the board using the Quartus II (6.0sp1), 
the download program seems all happy and returns with a "SUCCESS" message at 
the end of the process.  The board on the other end always contains the same 
NiosII implementation running uClinux!!!  Could it be that after the JTAG 
load is complete the FPGA resets and simply reloads the default application 
from the on-board configuration deice? 

Hi Jack,
  This post may be useful:
http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/27cd7423127f3bbb/1fbb4ad5554ab9ca?lnk=st&q=device+and+pin+subroto&rnum=2#1fbb4ad5554ab9ca

It deals with setting up Unused Pins for your projecs to the correct value.

Hope this helps,
Subroto Datta
Altera Corp.

"Jack Zkcmbcyk" <zkcmbcyk9@hotmail.com> wrote in message 
news:s5qNg.40493$8g4.523646@weber.videotron.net...
> Hello out there!
>
>   I have purchased an Altera Nios II Cyclone based (EP1C12F324) evalution 
> kit a while ago and didn't get to work with until recently.  At first I 
> was happy to see how quickly I got the board up and running and 
> interacting with my PC through an Ethernet LAN and serving web pages using 
> the uClinux on-board http server.
>
>   Having had enough of the demo I started developping an application of my 
> own.  I first downloaded (via the USB cable connector that provides a USB 
> Blaster interface) a very simple code file to start flashing the LEDs. 
> When that didn't work, I simplified the code to an even simpler test case 
> where only one LED was involved.  After that not even working, I started 
> combing through the documentation in search for some clues.  This is when 
> I noticed a lot of little discrepencies between the real board and the 
> document set.
>
>    To this day, I still haven't been able to get a simple LED to flash 
> (not even once).  I am getting a bit impatient with the whole thing and 
> might just go back to a Xilinx board that is sitting around my ofice. 
> Before I do that, I would like to know if any one out there has played 
> with this board and might have some hints for me.
>
>    Thanks in advance for any tid bits.
>
> P.S.  When I download the code to the board using the Quartus II (6.0sp1), 
> the download program seems all happy and returns with a "SUCCESS" message 
> at the end of the process.  The board on the other end always contains the 
> same NiosII implementation running uClinux!!!  Could it be that after the 
> JTAG load is complete the FPGA resets and simply reloads the default 
> application from the on-board configuration deice?
> 

Hello Subroto!

    That article did it.  I was able to revise my simple project, load it 
and got my LED to start flashing.  Thanks a lot.


"Subroto Datta" <    > wrote in message 
news:tQrNg.347$e66.257@newssvr13.news.prodigy.com...
> Hi Jack,
>  This post may be useful:
> http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/27cd7423127f3bbb/1fbb4ad5554ab9ca?lnk=st&q=device+and+pin+subroto&rnum=2#1fbb4ad5554ab9ca
>
> It deals with setting up Unused Pins for your projecs to the correct 
> value.
>
> Hope this helps,
> Subroto Datta
> Altera Corp.
>
> "Jack Zkcmbcyk" <zkcmbcyk9@hotmail.com> wrote in message 
> news:s5qNg.40493$8g4.523646@weber.videotron.net...
>> Hello out there!
>>
>>   I have purchased an Altera Nios II Cyclone based (EP1C12F324) evalution 
>> kit a while ago and didn't get to work with until recently.  At first I 
>> was happy to see how quickly I got the board up and running and 
>> interacting with my PC through an Ethernet LAN and serving web pages 
>> using the uClinux on-board http server.
>>
>>   Having had enough of the demo I started developping an application of 
>> my own.  I first downloaded (via the USB cable connector that provides a 
>> USB Blaster interface) a very simple code file to start flashing the 
>> LEDs. When that didn't work, I simplified the code to an even simpler 
>> test case where only one LED was involved.  After that not even working, 
>> I started combing through the documentation in search for some clues. 
>> This is when I noticed a lot of little discrepencies between the real 
>> board and the document set.
>>
>>    To this day, I still haven't been able to get a simple LED to flash 
>> (not even once).  I am getting a bit impatient with the whole thing and 
>> might just go back to a Xilinx board that is sitting around my ofice. 
>> Before I do that, I would like to know if any one out there has played 
>> with this board and might have some hints for me.
>>
>>    Thanks in advance for any tid bits.
>>
>> P.S.  When I download the code to the board using the Quartus II 
>> (6.0sp1), the download program seems all happy and returns with a 
>> "SUCCESS" message at the end of the process.  The board on the other end 
>> always contains the same NiosII implementation running uClinux!!!  Could 
>> it be that after the JTAG load is complete the FPGA resets and simply 
>> reloads the default application from the on-board configuration deice?
>>
>
>