Spartan3: Multiplier Madness

Hello everybody,

In a design I'm working on I want to multiply two 16 bit 2's
complement (signed) numbers using the mult18x18 multipliers. According
to the Sparten 3 userguide, it is enough to use the lower bits and
take the result from the output. However, when I do this, the result
is not correct when negative numbers are multiplied, positive numbers
are no problem.

If I use the highest (MSB) bits of the multiplier, the results are
correct. But... using the highest bits of the multiplier causes my
design to fail timing constraints because the multipliers get slower
when more bits are being used.

What am I doing wrong here?

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Nico Coesel <nico@puntnl.niks> wrote:
> Hello everybody,

> In a design I'm working on I want to multiply two 16 bit 2's
> complement (signed) numbers using the mult18x18 multipliers. According
> to the Sparten 3 userguide, it is enough to use the lower bits and
> take the result from the output. However, when I do this, the result
> is not correct when negative numbers are multiplied, positive numbers
> are no problem.

> If I use the highest (MSB) bits of the multiplier, the results are
> correct. But... using the highest bits of the multiplier causes my
> design to fail timing constraints because the multipliers get slower
> when more bits are being used.

> What am I doing wrong here?

Probably you need to sign-extend when stuffing the high bits...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Nico Coesel wrote:

>Hello everybody,
>
>In a design I'm working on I want to multiply two 16 bit 2's
>complement (signed) numbers using the mult18x18 multipliers. According
>to the Sparten 3 userguide, it is enough to use the lower bits and
>take the result from the output. However, when I do this, the result
>is not correct when negative numbers are multiplied, positive numbers
>are no problem.
>
>If I use the highest (MSB) bits of the multiplier, the results are
>correct. But... using the highest bits of the multiplier causes my
>design to fail timing constraints because the multipliers get slower
>when more bits are being used.
>
>What am I doing wrong here?
>
>  
>
Could you sign-extend the upper 2 bits, basically tie the bits 17, 16 and 15
together on both inputs?  It really then is still a 16-bit multiply.  On the
other hand, if the 2 LSB's are always zero, the propagation time shouldn't
get worse than if it was the 2 MSB's that are zero.

Jon

Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

>Nico Coesel <nico@puntnl.niks> wrote:
>> Hello everybody,
>
>> In a design I'm working on I want to multiply two 16 bit 2's
>> complement (signed) numbers using the mult18x18 multipliers. According
>> to the Sparten 3 userguide, it is enough to use the lower bits and
>> take the result from the output. However, when I do this, the result
>> is not correct when negative numbers are multiplied, positive numbers
>> are no problem.
>
>> If I use the highest (MSB) bits of the multiplier, the results are
>> correct. But... using the highest bits of the multiplier causes my
>> design to fail timing constraints because the multipliers get slower
>> when more bits are being used.
>
>> What am I doing wrong here?
>
>Probably you need to sign-extend when stuffing the high bits...

I tried that, but that didn't solve the problem and made meeting the
timing constrains even harder.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Nico Coesel wrote:
> Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote:
> 
> 
>>Nico Coesel <nico@puntnl.niks> wrote:
>>
>>>Hello everybody,
>>
>>>In a design I'm working on I want to multiply two 16 bit 2's
>>>complement (signed) numbers using the mult18x18 multipliers. According
>>>to the Sparten 3 userguide, it is enough to use the lower bits and
>>>take the result from the output. However, when I do this, the result
>>>is not correct when negative numbers are multiplied, positive numbers
>>>are no problem.
>>
>>>If I use the highest (MSB) bits of the multiplier, the results are
>>>correct. But... using the highest bits of the multiplier causes my
>>>design to fail timing constraints because the multipliers get slower
>>>when more bits are being used.
>>
>>>What am I doing wrong here?
>>
>>Probably you need to sign-extend when stuffing the high bits...
> 
> 
> I tried that, but that didn't solve the problem and made meeting the
> timing constrains even harder.
> 

Sign extend the inputs to the uper bits, but keep your active 16 bits in 
the bottom.  The timing analyzer doesn't figure out you have the bottom 
bits tied to zero, so it gives you timing for an 18x18 if you are taking 
outputs from the top bits of the product.  You might also consider 
registering the multiplier output with flip-flops and place them 
immediately adjacent to the multiplier rather than letting the 
auto-placement do it.  THe autoplace doesn't do so hot a job at placing 
registers around the multipliers, so you can fail timing due to a long 
route combined with the relatively slow clock to out of the multiplier.

The output timing is the more critical for a pipelined multiply.  You 
may also find you need to pipeline the inputs, in which case those 
should also be hand placed near the multiplier (but put the output 
registers closest) to get the peak performance.

On Thu, 2006-09-14 at 20:13 +0000, Nico Coesel wrote:
> Hello everybody,
> 
> In a design I'm working on I want to multiply two 16 bit 2's
> complement (signed) numbers using the mult18x18 multipliers. According
> to the Sparten 3 userguide, it is enough to use the lower bits and
> take the result from the output. However, when I do this, the result
> is not correct when negative numbers are multiplied, positive numbers
> are no problem.

Hi Nico,

I recently had a very similar problem.  The cause of my problem was that
I cut and paste the vhdl template and didn't change the library it was
uing.  So it was using the unsigned library!  Needless to say, that
didn't work too well.  I changed to using the signed library and it
worked fine.

Cheers,

James.

"James Morrison" <spam1@emorrison.ca> wrote in message 
news:1158283978.4061.39.camel@spice.emorrison.ca...
> uing.  So it was using the unsigned library!  Needless to say, that
> didn't work too well.  I changed to using the signed library and it
> worked fine.
>
> Cheers,
>
> James.
>
>
Hi James,

Only a multiplier madman would use other than numeric.std ! :-)

You might find Jim Lewis's excellent paper useful, I know I do.

http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

HTH, Syms. 

nico@puntnl.niks (Nico Coesel) wrote:

>Hello everybody,
>
>In a design I'm working on I want to multiply two 16 bit 2's
>complement (signed) numbers using the mult18x18 multipliers. According
>to the Sparten 3 userguide, it is enough to use the lower bits and
>take the result from the output. However, when I do this, the result
>is not correct when negative numbers are multiplied, positive numbers
>are no problem.
>
>If I use the highest (MSB) bits of the multiplier, the results are
>correct. But... using the highest bits of the multiplier causes my
>design to fail timing constraints because the multipliers get slower
>when more bits are being used.
>

Thanks for the responses. Extending the sign makes timing even worse
so I guess I'm stuck with using the top bits of the multiplier.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Can't you use a multi cycle constraint ?

On 15 Sep 2006 11:33:56 +0200, "Symon" <symon_brewer@hotmail.com>
wrote:

>"James Morrison" <spam1@emorrison.ca> wrote in message 
>news:1158283978.4061.39.camel@spice.emorrison.ca...
>> uing.  So it was using the unsigned library!  Needless to say, that
>> didn't work too well.  I changed to using the signed library and it
>> worked fine.
>>
>> Cheers,
>>
>> James.
>>
>>
>Hi James,
>
>Only a multiplier madman would use other than numeric.std ! :-)
>
>You might find Jim Lewis's excellent paper useful, I know I do.
>
>http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Thanks for the pointer to the paper, Symon.  

MAPLD always has some interesting presentations.  One of these days
I'm going to attend, provided my cheap boss will pay for the trip.

Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com