Forums

problems with IOSTANDARD

Started by Martin Geisse September 15, 2006
Hi to all,

I'm trying to set the output voltage level of a Virtex 2 pro using the
IOSTANDARD constraint, but it doesn't work.

More exactly, I'm using the XUP Virtex-II Pro Development System (an
evaluation board) by Xilinx. For an application, I need the FPGA to
output 3.3 V signals on the left low-speed expansion connector. I have
tried to achieve this by placing the following lines in my UCF file
(using one of the signals as an example):

NET "camera_sio_d" LOC = "U3";
NET "camera_sio_d" IOSTANDARD = LVTTL;

However, the FPGA outputs 2.5 V for digital 1 (0 V for digital 0),
measured with no load on the signal. I have tried different values for
IOSTANDARD as an experiment (LVTTL, LVCMOS33, LVCMOS15, and omitting the
constaint altogether), but nothing happens - I still get 2.5 V. The
scope is fast enough, and by tweaking the timing a bit I can say that
these voltage levels are stable (no capacity being charged anymore). The
voltage supply for the whole board also seems to be okay. Note that even
LVCMOS15 (which should give me 1.5 V) doesn't work, so I don't think
it's an electrical problem.

To avoid problems with banking rules for the pins, I have set all pins
on the relevant bank to the levels described above. The implementation
tools do complain if the IOSTANDARD of different pins on the same bank
mismatch, so I think I'm not doing this anymore. To be sure, I have
looked at the pad report, and also viewd the placed and routed
configuration in the FPGA editor. Both tell me that the IOSTANDARD is
indeed set to the value I want. Still I get 2.5 V when programming the
real FPGA.

Thanks in advance for any ideas.

Martin Geisse
Martin,
You can only use certain I/O standards with specific Vccos. If you want to 
change voltage, you must change both the I/O standard and Vcco. Read the 
manual about the I/O banking rules.
HTH, Syms. 


Symon wrote:
> Martin, > You can only use certain I/O standards with specific Vccos. If you want to > change voltage, you must change both the I/O standard and Vcco. Read the > manual about the I/O banking rules. > HTH, Syms.
To expand a little, if you have an output buffer powered by 2.5 volts, how do you expect the FPGA to get up to 3.3V?

Martin Geisse wrote:

> Hi to all, > > I'm trying to set the output voltage level of a Virtex 2 pro using the > IOSTANDARD constraint, but it doesn't work. > > More exactly, I'm using the XUP Virtex-II Pro Development System (an > evaluation board) by Xilinx. For an application, I need the FPGA to > output 3.3 V signals on the left low-speed expansion connector. I have > tried to achieve this by placing the following lines in my UCF file > (using one of the signals as an example): > > NET "camera_sio_d" LOC = "U3"; > NET "camera_sio_d" IOSTANDARD = LVTTL; > > However, the FPGA outputs 2.5 V for digital 1 (0 V for digital 0), > measured with no load on the signal.
What is the power supply to the Vccext on that bank? If it is 2.5 V, you can play with the IO spec all you want, there's no way it can produce 3.3 V. You may have to change a regulator, move jumpers, or whatever to get 3.3 V to that bank's power supply. Jon
On 15 Sep 2006 14:38:26 +0200, "Symon" <symon_brewer@hotmail.com> wrote:

>Martin, >You can only use certain I/O standards with specific Vccos. If you want to >change voltage, you must change both the I/O standard and Vcco. Read the >manual about the I/O banking rules. >HTH, Syms. >
There are quite a lot of manuals, and quite a lot of reading... sometimes even finding what you want in all the available literature is quite an achievement. where would you suggest the reader should start for a good outline of the I/O banking rules? I don't know if the OP wuold appreciate such a hint, but I confess I would. - Brian
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message 
news:3fong21thj450qaqdharsmgkcjv7oiedhk@4ax.com...
> On 15 Sep 2006 14:38:26 +0200, "Symon" <symon_brewer@hotmail.com> wrote: > >>Martin, >>You can only use certain I/O standards with specific Vccos. If you want to >>change voltage, you must change both the I/O standard and Vcco. Read the >>manual about the I/O banking rules. >>HTH, Syms. >> > > There are quite a lot of manuals, and quite a lot of reading... > sometimes even finding what you want in all the available literature is > quite an achievement. > > where would you suggest the reader should start for a good outline of > the I/O banking rules? > > I don't know if the OP wuold appreciate such a hint, but I confess I > would. > > - Brian
Hi Brian, You're right, the Xilinx literature can be an insomniac's delight! In this case however, the data is right where you'd expect it. Get DS083, the VII-Pro datasheet, under functional description, FPGA, IOBs, there's a table called 'Supported Single-Ended I/O Standards.'. A little below that is a whole section called 'I/O Banking'. HTH, Syms.
John_H wrote:
> Symon wrote: > >> Martin, >> You can only use certain I/O standards with specific Vccos. If you >> want to change voltage, you must change both the I/O standard and >> Vcco. Read the manual about the I/O banking rules. >> HTH, Syms. > > > > To expand a little, if you have an output buffer powered by 2.5 volts, > how do you expect the FPGA to get up to 3.3V?
Thanks to you and others for your quick reply. I think I understand now what confused me first, but it would be nice if you could tell me if I am right on this: If Vcco is connected to 2.5 V, is it then impossible to get down to 1.5 V output level by using LVCMOS15? (I do not want to output 1.5 V in my final design. Using LVCMOS15 was an experiment to see whether I can alter the output level at all. Although I understand that I cannot produce any higher level than Vcco, my assumption was that producing a lower level is possible. Since the level did not change to 1.5, this experiment led me to the conclusion that Vcco is not the cause of the problem, and that something went wrong with the toolchain, but I'm no longer sure about this). Thanks, Martin Geisse
Martin Geisse schrieb:

> John_H wrote: > > Symon wrote: > > > >> Martin, > >> You can only use certain I/O standards with specific Vccos. If you > >> want to change voltage, you must change both the I/O standard and > >> Vcco. Read the manual about the I/O banking rules. > >> HTH, Syms. > > > > > > > > To expand a little, if you have an output buffer powered by 2.5 volts, > > how do you expect the FPGA to get up to 3.3V? > > Thanks to you and others for your quick reply. I think I understand now > what confused me first, but it would be nice if you could tell me if I > am right on this: If Vcco is connected to 2.5 V, is it then impossible > to get down to 1.5 V output level by using LVCMOS15? > > (I do not want to output 1.5 V in my final design. Using LVCMOS15 was an > experiment to see whether I can alter the output level at all. Although > I understand that I cannot produce any higher level than Vcco, my > assumption was that producing a lower level is possible. Since the level > did not change to 1.5, this experiment led me to the conclusion that > Vcco is not the cause of the problem, and that something went wrong with > the toolchain, but I'm no longer sure about this). > > Thanks, > Martin Geisse
the output level will match the actual VCCIO on that bank, no matter the IOSTANDARD setting. Antti
On 16 Sep 2006 14:05:55 +0200, "Symon" <symon_brewer@hotmail.com> wrote:

>"Brian Drummond" <brian_drummond@btconnect.com> wrote in message >news:3fong21thj450qaqdharsmgkcjv7oiedhk@4ax.com... >> On 15 Sep 2006 14:38:26 +0200, "Symon" <symon_brewer@hotmail.com> wrote: >> >>>Read the >>>manual about the I/O banking rules. >>>HTH, Syms. >> >> There are quite a lot of manuals, and quite a lot of reading... >> sometimes even finding what you want in all the available literature is >> quite an achievement.
>Hi Brian, >You're right, the Xilinx literature can be an insomniac's delight! >In this case however, the data is right where you'd expect it. Get DS083, >the VII-Pro datasheet, under functional description, FPGA, IOBs, there's a >table called 'Supported Single-Ended I/O Standards.'. A little below that is >a whole section called 'I/O Banking'. >HTH, Syms.
Thanks! Glad it sometimes works... Actually I confess to having reached the download stage on DS083 several times on several different issues, and been told the file already exists... you'd think I'd learn! Now if only the support database was searchable for INFO:XST:1943 and other obscure messages. Such as WARNING:Xst:638 and 1303, which translate to "KEEP attribute detected; deleting signal anyway" without giving a clue about the problem... - Brian
Antti wrote:
> [...] > > the output level will match the actual VCCIO on that bank, > no matter the IOSTANDARD setting. > > > Antti
Okay, thanks a lot for your help! Martin