Writing VHDL, Software dummy!

I have a couple of questions regarding VHDL and FPGAs as I am starting
a project on them shortly0.  Before I start I would  like to apologize
for my lack of knowledge on them.  I am a software developer not a
hardware so you might have to take this into consideration when
explaining.

I know VHDL is a hardware description language, but what is the biggest
challenge when writing code in VHDL compared to for example C.

Is it writing your code as close to elemtary logic as possible(that
will result in efficiency)??
Or is it perhaps timing challenges?

As you can see I am pretty fresh and I will dig down in VHDL literature
pretty soon but I would appreaciate a little input from people who are
experienced in it before I start. 

Cheers,
Chris

chadl...@online.no schrieb:

> I have a couple of questions regarding VHDL and FPGAs as I am starting
> a project on them shortly0.  Before I start I would  like to apologize
> for my lack of knowledge on them.  I am a software developer not a
> hardware so you might have to take this into consideration when
> explaining.
>
> I know VHDL is a hardware description language, but what is the biggest
> challenge when writing code in VHDL compared to for example C.

you do not write code in VHDL
,
in VHDL you __describe__ the hardware.

thats the difference, you are not programming as VHDL is not a
programming language, you are describing the hardware you want to be
implemented.

this is the first thing you have to understand.

Antti

On 18 Sep 2006 04:36:31 -0700, "Antti" <Antti.Lukats@xilant.com> wrote:

>chadl...@online.no schrieb:
>
>> I have a couple of questions regarding VHDL and FPGAs as I am starting
>> a project on them shortly0.  Before I start I would  like to apologize
>> for my lack of knowledge on them.  I am a software developer not a
>> hardware so you might have to take this into consideration when
>> explaining.
>>
>> I know VHDL is a hardware description language, but what is the biggest
>> challenge when writing code in VHDL compared to for example C.
>
>you do not write code in VHDL
>,
>in VHDL you __describe__ the hardware.
>
>thats the difference, you are not programming as VHDL is not a
>programming language, you are describing the hardware you want to be
>implemented.

..so you have to have at least a reasonable idea of the hardware design and functionality you are
trying to describe. 

Having said that, once you get your head round the basic concepts, you can write code that starts to
look and behave rather like software..... this can be a good or bad thing...

chadland@online.no wrote:

> I have a couple of questions regarding VHDL and FPGAs as I am starting
> a project on them shortly0.  Before I start I would  like to apologize
> for my lack of knowledge on them.  I am a software developer not a
> hardware so you might have to take this into consideration when
> explaining.
> 
> I know VHDL is a hardware description language, but what is the biggest
> challenge when writing code in VHDL compared to for example C.
> 
Firstly, don't link HDL and software in this Newgroup. HDL purists are very
fanatical about maintaining a distinction between the two. However, you do
write VHDL in text files. Oh, and not all HDL's are "written".

The biggest challenge developing with VHDL is it's verbose nature (which
stems from it's root language: ADA). If you have written in C and find that
language easy, may I suggest Verilog instead of VHDL. BTW VHDL is the
favourite with the US/UK Military. Next challenge for most software
developers is coming to terms with the parallel nature of a HDL.

> Is it writing your code as close to elemtary logic as possible(that
> will result in efficiency)??
Not an easy question... As a programmer maybe this answer will better fit
you: Not all compilers produce efficient object/machine code from the same
source code.

Also, describing your system with elementary VHDL behaviours (in most cases
today) will waste resources on the target programmable logic device. Thus:
A 8Kbit memory module described in HDL would be portable between vendor
silicon, but resource hungry. A more resource efficient implementation is
gained using vendor specific HDL functions, that in turn use existing PLD
onchip memory (BlockRam SelectRAM etc).

> Or is it perhaps timing challenges?
> 
Timing challenges are the most involved aspect of digital electronics, no
less the PLD field. Especially when autorouting results in domain skew on
your system (synchronisation) clock.


> As you can see I am pretty fresh and I will dig down in VHDL literature
> pretty soon but I would appreaciate a little input from people who are
> experienced in it before I start.
> 
I would suggest a $99-$199 dev kit from Altera or Xilinx. They both have
free downloadable tools:
http://www.altera.com/products/devkits/partners/kit-alt-live-design.html
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US

> Cheers,
> Chris

Thanks for the rapid replies. You guys have been very helpfull. During
my project phase I will use this forum frequently(without trying to ask
to many stupid questions of course :) ).

Cheers,
Chris Hadland, Laerdal Medical AS

Chris,
One of the comments made by Dave:  "Next challenge for most software
developers is coming to terms with the parallel nature of a HDL."
represents a significant divergence between software implementation of
logic and hardware implementation of logic.  In software, with a single
processor, all logic is evaluated sequentially from the start of the
program to the end of the program.  In hardware, if you think about it,
the whole FPGA is operating simultaneously.  You have to describe the
logic sequentially because that's the nature of the physical media (eg
the text file), but the hardware it describes is all present once the
power is turned on.  That dimensional shift can take a little getting
used to.