Lattice .bit file format

Hi,

Does anybody know the internal structure of a Lattice .bit file? I
do a CPU design including RAM and ROM for the CPU inside the FPGA.
I am currently working on the firmware and every time I make a new
version of the CPU program I have to integrate it into ispLEVER and
recompile the whole FPGA to generate the .bit file, which takes
about 8 minutes on my PC, which is a real pain.
Is there any way to insert the contents of the ROM (implemented as
EBR blocks) into the .bit file directly?
Or is there any other way to do this?
I am using a LFECP33E chip on an "HPEmini" development board.

Thanks a lot,

Johannes

Johannes Hausensteiner schrieb:

> Hi,
>
> Does anybody know the internal structure of a Lattice .bit file? I
> do a CPU design including RAM and ROM for the CPU inside the FPGA.
> I am currently working on the firmware and every time I make a new
> version of the CPU program I have to integrate it into ispLEVER and
> recompile the whole FPGA to generate the .bit file, which takes
> about 8 minutes on my PC, which is a real pain.
> Is there any way to insert the contents of the ROM (implemented as
> EBR blocks) into the .bit file directly?
> Or is there any other way to do this?
> I am using a LFECP33E chip on an "HPEmini" development board.
>
> Thanks a lot,
>
> Johannes

there is a network reference design at lattice website with Z80
cpu a networking stuff, I think it includes some script to update
the bt file as well.

Antti

Hi,
Thank you for your hint. Unfortunately I am not able to find the
mentioned reference design. Can you provide a link?
Thanks again,

Johannes

Antti wrote:
> Johannes Hausensteiner schrieb:
> 
>> Hi,
>>
>> Does anybody know the internal structure of a Lattice .bit file? I
>> do a CPU design including RAM and ROM for the CPU inside the FPGA.
>> I am currently working on the firmware and every time I make a new
>> version of the CPU program I have to integrate it into ispLEVER and
>> recompile the whole FPGA to generate the .bit file, which takes
>> about 8 minutes on my PC, which is a real pain.
>> Is there any way to insert the contents of the ROM (implemented as
>> EBR blocks) into the .bit file directly?
>> Or is there any other way to do this?
>> I am using a LFECP33E chip on an "HPEmini" development board.
>>
>> Thanks a lot,
>>
>> Johannes
> 
> there is a network reference design at lattice website with Z80
> cpu a networking stuff, I think it includes some script to update
> the bt file as well.
> 
> Antti
> 

Johannes Hausensteiner schrieb:

> Hi,
> Thank you for your hint. Unfortunately I am not able to find the
> mentioned reference design. Can you provide a link?
> Thanks again,
>
> Johannes
>
> Antti wrote:
> > Johannes Hausensteiner schrieb:
> >
> >> Hi,
> >>
> >> Does anybody know the internal structure of a Lattice .bit file? I
> >> do a CPU design including RAM and ROM for the CPU inside the FPGA.
> >> I am currently working on the firmware and every time I make a new
> >> version of the CPU program I have to integrate it into ispLEVER and
> >> recompile the whole FPGA to generate the .bit file, which takes
> >> about 8 minutes on my PC, which is a real pain.
> >> Is there any way to insert the contents of the ROM (implemented as
> >> EBR blocks) into the .bit file directly?
> >> Or is there any other way to do this?
> >> I am using a LFECP33E chip on an "HPEmini" development board.
> >>
> >> Thanks a lot,
> >>
> >> Johannes
> >
> > there is a network reference design at lattice website with Z80
> > cpu a networking stuff, I think it includes some script to update
> > the bt file as well.
> >
> > Antti
> >
http://www.latticesemi.com/products/intellectualproperty/ipcores/trispeedethernetmediaacce/trispeedethernetmacdemofo.cfm

Antti

Works great! thanks!

Antti wrote:
> Johannes Hausensteiner schrieb:
> 
>> Hi,
>> Thank you for your hint. Unfortunately I am not able to find the
>> mentioned reference design. Can you provide a link?
>> Thanks again,
>>
>> Johannes
>>
>> Antti wrote:
>>> Johannes Hausensteiner schrieb:
>>>
>>>> Hi,
>>>>
>>>> Does anybody know the internal structure of a Lattice .bit file? I
>>>> do a CPU design including RAM and ROM for the CPU inside the FPGA.
>>>> I am currently working on the firmware and every time I make a new
>>>> version of the CPU program I have to integrate it into ispLEVER and
>>>> recompile the whole FPGA to generate the .bit file, which takes
>>>> about 8 minutes on my PC, which is a real pain.
>>>> Is there any way to insert the contents of the ROM (implemented as
>>>> EBR blocks) into the .bit file directly?
>>>> Or is there any other way to do this?
>>>> I am using a LFECP33E chip on an "HPEmini" development board.
>>>>
>>>> Thanks a lot,
>>>>
>>>> Johannes
>>> there is a network reference design at lattice website with Z80
>>> cpu a networking stuff, I think it includes some script to update
>>> the bt file as well.
>>>
>>> Antti
>>>
> http://www.latticesemi.com/products/intellectualproperty/ipcores/trispeedethernetmediaacce/trispeedethernetmacdemofo.cfm
> 
> Antti
> 

Johannes,

Lattice's current software, ispLEVER 6.0 does offer the ability to
reinitialize your memory contents without recompiling your design.
Using the Memory Initialization tool, accessed from the tools menu, a
new, or modified memory file .mem can be written to the designs
database file .ncd.  After this is done all that needs to be rerun is
the 'Generate Bitstream Data' process.  This feature is only available
for use on memory blocks that are implemented in the devices EBR blocks
and created using the software's IPExpress module generation tool.

Kevin schrieb:

> Johannes,
>
> Lattice's current software, ispLEVER 6.0 does offer the ability to
> reinitialize your memory contents without recompiling your design.
> Using the Memory Initialization tool, accessed from the tools menu, a
> new, or modified memory file .mem can be written to the designs
> database file .ncd.  After this is done all that needs to be rerun is
> the 'Generate Bitstream Data' process.  This feature is only available
> for use on memory blocks that are implemented in the devices EBR blocks
> and created using the software's IPExpress module generation tool.

is the memory init available from commandline also?
the GUI tool is known to exist for some time, the commandline
bit file merging is far less documented

Antti

Yes, it can be run via commandline.  In the ispLEVER help do a search
for 'memedit', this is the memory initialization tool executable.  In
the search results select 'Running MEMEDIT from the Command Line' to
open the MEMEDIT help page.

Kevin


Antti wrote:
> Kevin schrieb:
>
> > Johannes,
> >
> > Lattice's current software, ispLEVER 6.0 does offer the ability to
> > reinitialize your memory contents without recompiling your design.
> > Using the Memory Initialization tool, accessed from the tools menu, a
> > new, or modified memory file .mem can be written to the designs
> > database file .ncd.  After this is done all that needs to be rerun is
> > the 'Generate Bitstream Data' process.  This feature is only available
> > for use on memory blocks that are implemented in the devices EBR blocks
> > and created using the software's IPExpress module generation tool.
>
> is the memory init available from commandline also?
> the GUI tool is known to exist for some time, the commandline
> bit file merging is far less documented
> 
> Antti

I got the following procedure from the mentioned reference design:

%LATTICE_HOME%\ispFPGA\bin\nt\memedit.exe ROMFILE.mem FPGA_PROJECT.ncd 
MODULE.lpc INSTANTIATION_NAME

%LATTICE_HOME%\ispFPGA\bin\nt\bitgen -w -g RamCfg:Reset FPGA_PROJECT.ncd 
FPGA_PROJECT.bit FPGA_PROJECT.prf

This takes about 1 minute compared to 8 minutes for the whole FPGA
design.

I made a conversion utility which converts from a standard Intel
HEX file to the .mem format ('addressed hex'). You can download
it from here:
    http://diycalculator.pcl.at/images/a/a3/Hex2mem-1.0.tar.gz

Thanks again for the fast help!

Johannes


Kevin wrote:
> Yes, it can be run via commandline.  In the ispLEVER help do a search
> for 'memedit', this is the memory initialization tool executable.  In
> the search results select 'Running MEMEDIT from the Command Line' to
> open the MEMEDIT help page.
> 
> Kevin
> 
> 
> Antti wrote:
>> Kevin schrieb:
>>
>>> Johannes,
>>>
>>> Lattice's current software, ispLEVER 6.0 does offer the ability to
>>> reinitialize your memory contents without recompiling your design.
>>> Using the Memory Initialization tool, accessed from the tools menu, a
>>> new, or modified memory file .mem can be written to the designs
>>> database file .ncd.  After this is done all that needs to be rerun is
>>> the 'Generate Bitstream Data' process.  This feature is only available
>>> for use on memory blocks that are implemented in the devices EBR blocks
>>> and created using the software's IPExpress module generation tool.
>> is the memory init available from commandline also?
>> the GUI tool is known to exist for some time, the commandline
>> bit file merging is far less documented
>>
>> Antti
> 

On 2006-09-22, Johannes Hausensteiner <johannes.hausensteiner@pcl.at> wrote:
> I got the following procedure from the mentioned reference design:
>
> %LATTICE_HOME%\ispFPGA\bin\nt\memedit.exe ROMFILE.mem FPGA_PROJECT.ncd 
> MODULE.lpc INSTANTIATION_NAME
>
> %LATTICE_HOME%\ispFPGA\bin\nt\bitgen -w -g RamCfg:Reset FPGA_PROJECT.ncd 
> FPGA_PROJECT.bit FPGA_PROJECT.prf

Is it just me or are the file extensions, commands and options very
similar to the ones used in Xilinx' ISE flow?

/Andreas