I am searching for a new topic related to FPGAs and that is publishable? Any ideas? I was thinking of area, performance, speed and interconnection optimization. Please provide me with some interesting ideas and I will do the rest of the work. Thanks!
PUBLISHABLE PAPER RELATED TO FPGA!
Started by ●September 26, 2006
Reply by ●September 26, 20062006-09-26
solo wrote:> I am searching for a new topic related to FPGAs and that is > publishable? > Any ideas? > I was thinking of area, performance, speed and interconnection > optimization. Please provide me with some interesting ideas and I will > do the rest of the work. > Thanks! >Any improvements that can be made in the place + route burden would be publishable, as well as make you $$$. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architecture
Reply by ●September 26, 20062006-09-26
Hey Dave, Can you be more specific in your advice please? Thanks! David Ashley wrote:> solo wrote: > > I am searching for a new topic related to FPGAs and that is > > publishable? > > Any ideas? > > I was thinking of area, performance, speed and interconnection > > optimization. Please provide me with some interesting ideas and I will > > do the rest of the work. > > Thanks! > > > > Any improvements that can be made in the place + route > burden would be publishable, as well as make you $$$. > > -Dave > > -- > David Ashley http://www.xdr.com/dash > Embedded linux, device drivers, system architecture
Reply by ●September 26, 20062006-09-26
solo wrote:> I am searching for a new topic related to FPGAs and that is > publishable? > Any ideas? > I was thinking of area, performance, speed and interconnection > optimization. Please provide me with some interesting ideas and I will > do the rest of the work. > Thanks!how about single inline fpga which use veroboard spacing, and can be broken off at one pin intervals. place 4 pins in prigrammer for power, clk, and program data, and then break off to length specified by fpga compilier. available in 1m strips maybe. needs comparator for analog input, and as much logic in 1 pin segment as possible. flash on board prefered, with some 4 cycle dram too, for compactness. is this the kind of thing u meant??
Reply by ●September 26, 20062006-09-26
This gives a whole new meaning to the term "partial reconfiguration" Todd jacko wrote:> how about single inline fpga which use veroboard spacing, and can be > broken off at one pin intervals. > > place 4 pins in prigrammer for power, clk, and program data, and then > break off to length specified by fpga compilier. > > > available in 1m strips maybe. > > > needs comparator for analog input, and as much logic in 1 pin segment > as possible. > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > is this the kind of thing u meant??
Reply by ●September 26, 20062006-09-26
We may have to teach Mr Solo some basic facts: First you must have an interesting idea or some valuable specific knowledge. Then, and only then, do you start writing an article. He seems to have this ass-backwards. Beyond that it might also be wise not to insult this newsgroup with arrogant statements about the lust for capitalization. Peter Alfke ============= Todd Fleming wrote:> This gives a whole new meaning to the term "partial reconfiguration" > > Todd > > jacko wrote: > > how about single inline fpga which use veroboard spacing, and can be > > broken off at one pin intervals. > > > > place 4 pins in prigrammer for power, clk, and program data, and then > > break off to length specified by fpga compilier. > > > > > > available in 1m strips maybe. > > > > > > needs comparator for analog input, and as much logic in 1 pin segment > > as possible. > > > > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > > > > is this the kind of thing u meant??
Reply by ●September 26, 20062006-09-26
Todd Fleming wrote:> This gives a whole new meaning to the term "partial reconfiguration" > > Toddsure does> jacko wrote: > > how about single inline fpga which use veroboard spacing, and can be > > broken off at one pin intervals. > > > > place 4 pins in prigrammer for power, clk, and program data, and then > > break off to length specified by fpga compilier. > > > > > > available in 1m strips maybe. > > > > > > needs comparator for analog input, and as much logic in 1 pin segment > > as possible. > > > > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > > > > is this the kind of thing u meant??if the pin ga to pin ga joints are flexi then 10m reels may be more gerber amenable. i think it could work. another great public domain idea provided by K Ring Technologies Semiconductor http://indi.joox.net
Reply by ●September 26, 20062006-09-26
"jacko" <jackokring@gmail.com> wrote in message news:1159302368.009079.245040@k70g2000cwa.googlegroups.com...> > solo wrote: >> I am searching for a new topic related to FPGAs and that is >> publishable? >> Any ideas? >> I was thinking of area, performance, speed and interconnection >> optimization. Please provide me with some interesting ideas and I will >> do the rest of the work. >> Thanks! > > how about single inline fpga which use veroboard spacing, and can be > broken off at one pin intervals. > > place 4 pins in prigrammer for power, clk, and program data, and then > break off to length specified by fpga compilier. > > > available in 1m strips maybe. > > > needs comparator for analog input, and as much logic in 1 pin segment > as possible. > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > is this the kind of thing u meant?? >i THINK IT SHOULD BE A m�BIUS STRIP fpga. sPECIFICALLY, A fpga SHAPED LIKE A m�BIUS STRIP. tO BE PRECISE, A TWO DIMENSIONAL kLEIN BOTTLE. i URGE YOU TO UPDATE YOUR UNDERSTANDING OF MY CLEAR AND ACCCURATE ADVICE. hth< YOURS 7TC< sYMSX
Reply by ●September 26, 20062006-09-26
Symon wrote:> "jacko" <jackokring@gmail.com> wrote in message > news:1159302368.009079.245040@k70g2000cwa.googlegroups.com... > > > > solo wrote: > >> I am searching for a new topic related to FPGAs and that is > >> publishable? > >> Any ideas? > >> I was thinking of area, performance, speed and interconnection > >> optimization. Please provide me with some interesting ideas and I will > >> do the rest of the work. > >> Thanks! > > > > how about single inline fpga which use veroboard spacing, and can be > > broken off at one pin intervals. > > > > place 4 pins in prigrammer for power, clk, and program data, and then > > break off to length specified by fpga compilier. > > > > > > available in 1m strips maybe. > > > > > > needs comparator for analog input, and as much logic in 1 pin segment > > as possible. > > > > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > > > > is this the kind of thing u meant?? > > > i THINK IT SHOULD BE A m=F6BIUS STRIP fpga. sPECIFICALLY, A fpga SHAPED L=IKE A> m=F6BIUS STRIP. tO BE PRECISE, A TWO DIMENSIONAL kLEIN BOTTLE. i URGE YOU=TO> UPDATE YOUR UNDERSTANDING OF MY CLEAR AND ACCCURATE ADVICE. > hth< YOURS 7TC< sYMSXleads to problems of orientability. i have studied topology in the mathematical sense. paypal donations to k ring tech semi using : jackokring@yahoo.com email. would also help in transfering my webserver to another space (50mb) as no budget at moment. also looking for funding to get an office off the ground, profit share a possibility.
Reply by ●September 26, 20062006-09-26
solo wrote:> David Ashley wrote: > >>solo wrote: >> >>>I am searching for a new topic related to FPGAs and that is >>>publishable? >>>Any ideas? >>>I was thinking of area, performance, speed and interconnection >>>optimization. Please provide me with some interesting ideas and I will >>>do the rest of the work. >>>Thanks! >>> >> >>Any improvements that can be made in the place + route >>burden would be publishable, as well as make you $$$. >> >>-Dave > Hey Dave, > > Can you be more specific in your advice please? > > Thanks!I'm told there haven't been any improvements to the place + route for the last 15 years, most of the improvements have been in integrating lots of different applications into single ones. Place + route = what has to be done automatically to map a netlist to actual fpga hardware. It is extremely computationally intensive. If you can improve the process, perhaps utilize fpga's to accelerate it somehow...people will be interested. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architecture
