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Configuration of Spartan 3 devices

Started by Dolphin September 27, 2006
Hello,

I am considering to use Spartan 3 devices on our new board. Xilinx
recommends XCF04S and XCF08P devices for configuration of a Spartan 3
1000. Does anybody know other and cheaper configuration solutions for
this FPGA?

thanks and best regards,
Dolphin

Dolphin schrieb:

> Hello, > > I am considering to use Spartan 3 devices on our new board. Xilinx > recommends XCF04S and XCF08P devices for configuration of a Spartan 3 > 1000. Does anybody know other and cheaper configuration solutions for > this FPGA? > > thanks and best regards, > Dolphin
6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash connect SPI DO to DIN, CCLK to SPI CLK, and let the micro to shift in read instruction and release prog_b then, s3 will configure in master serial mode. antti
On 27 Sep 2006 02:03:55 -0700, "Antti" <Antti.Lukats@xilant.com> wrote:

>Dolphin schrieb: > >> Hello, >> >> I am considering to use Spartan 3 devices on our new board. Xilinx >> recommends XCF04S and XCF08P devices for configuration of a Spartan 3 >> 1000. Does anybody know other and cheaper configuration solutions for >> this FPGA? >> >> thanks and best regards, >> Dolphin >6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash
or 9536XL CPLD if you need more speed, not much more expensive
Mike Harrison schrieb:
>>>I am considering to use Spartan 3 devices on our new board. Xilinx
>>6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash > > or 9536XL CPLD if you need more speed, not much more expensive
Or simply use Spartan3E, which can directly interface to cheap SPI Flash? Regards Falk
Mike Harrison schrieb:

> On 27 Sep 2006 02:03:55 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: > > >Dolphin schrieb: > > > >> Hello, > >> > >> I am considering to use Spartan 3 devices on our new board. Xilinx > >> recommends XCF04S and XCF08P devices for configuration of a Spartan 3 > >> 1000. Does anybody know other and cheaper configuration solutions for > >> this FPGA? > >> > >> thanks and best regards, > >> Dolphin > >6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash > or 9536XL CPLD if you need more speed, not much more expensive
the speed of the micro is ir-relevant, the FPGA generates the CCLK! thats the beaty, cheapest smallest micro is enough, you only pushin the read command, and let the FPGA todo the rest. the bitstream can embedded CCLK frequency to swithc to higher configuration clock. XC9536 are cheap too, but even in smallest package they are rather large compared to tiny micros in QFN 11 or SOT package Antti
Falk Brunner schrieb:

> Mike Harrison schrieb: > >>>I am considering to use Spartan 3 devices on our new board. Xilinx > > >>6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash > > > > or 9536XL CPLD if you need more speed, not much more expensive > > Or simply use Spartan3E, which can directly interface to cheap SPI Flash? > > Regards > Falk
well the OP wanted S3 so thats not an option, sure S3E, S3A, V5 all support direct SPI config Antti
Antti schrieb:

> well the OP wanted S3 so thats not an option,
Is it? Says who? I did not hear anything from the OP that prevents the use of a S3E. There are many ways to skin a cat. ;-) Regardas Falk
Antti wrote:
> Mike Harrison schrieb: > > > On 27 Sep 2006 02:03:55 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: > > > > >Dolphin schrieb: > > > > > >> Hello, > > >> > > >> I am considering to use Spartan 3 devices on our new board. Xilinx > > >> recommends XCF04S and XCF08P devices for configuration of a Spartan 3 > > >> 1000. Does anybody know other and cheaper configuration solutions for > > >> this FPGA? > > >> > > >> thanks and best regards, > > >> Dolphin > > >6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash > > or 9536XL CPLD if you need more speed, not much more expensive > > the speed of the micro is ir-relevant, the FPGA generates the CCLK! > thats the beaty, cheapest smallest micro is enough, you only pushin > the read command, and let the FPGA todo the rest.
Better make sure the SPI device has a continuous array read command. If you need to read per page, this technique won't work. By the way this sounds like you would need a little bit of extra logic to mux CCLK to the flash? Or were you supposing that the micro would push the command while the CCLK was free-running to the flash? Even at the startup CCLK speed that might require something a little faster than the cheapest smallest micro?
> > the bitstream can embedded CCLK frequency to swithc to higher > configuration clock. > > XC9536 are cheap too, but even in smallest package they are rather > large compared > to tiny micros in QFN 11 or SOT package > > Antti
Falk Brunner schrieb:

> Antti schrieb: > > > well the OP wanted S3 so thats not an option, > > Is it? Says who? I did not hear anything from the OP that prevents the > use of a S3E. There are many ways to skin a cat. ;-) > > Regardas > Falk
OP wanted solution for S3, not for S3e for S3e the SPI flash is obvious, and I bet Xilinx FAE would have suggested it, so I must assume that the S3e wasnt an option and solution was really required for S3 equally well I could say that solution is to use Cyclone or LatticeEC PFGA's as both support SPI loading and are comparable in size to Spartan-3, eg larger than larger device in Spartan3e Antti
Gabor schrieb:

> Antti wrote: > > Mike Harrison schrieb: > > > > > On 27 Sep 2006 02:03:55 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: > > > > > > >Dolphin schrieb: > > > > > > > >> Hello, > > > >> > > > >> I am considering to use Spartan 3 devices on our new board. Xilinx > > > >> recommends XCF04S and XCF08P devices for configuration of a Spartan 3 > > > >> 1000. Does anybody know other and cheaper configuration solutions for > > > >> this FPGA? > > > >> > > > >> thanks and best regards, > > > >> Dolphin > > > >6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash > > > or 9536XL CPLD if you need more speed, not much more expensive > > > > the speed of the micro is ir-relevant, the FPGA generates the CCLK! > > thats the beaty, cheapest smallest micro is enough, you only pushin > > the read command, and let the FPGA todo the rest. > > Better make sure the SPI device has a continuous array read > command. If you need to read per page, this technique won't > work. By the way this sounds like you would need a little bit > of extra logic to mux CCLK to the flash? Or were you supposing > that the micro would push the command while the CCLK was > free-running to the flash? Even at the startup CCLK speed that > might require something a little faster than the cheapest smallest > micro? > > > > > the bitstream can embedded CCLK frequency to swithc to higher > > configuration clock. > > > > XC9536 are cheap too, but even in smallest package they are rather > > large compared > > to tiny micros in QFN 11 or SOT package > > > > Antti
the micro holds PROG_B active so CCLK is tristated. it takes a few clock cycles of the MCU to shift in the array read and then all it has to be done is to make release the PROG_B the FPGA does the rest at config speed programmed into the BIT file Antti