Nios II dev board

Hi everybody,
I started to develop my fir filter with Quartus and Nios II dev board,
with an Altera Stratix II EP2S60ES.

The problems are starting now, when I'm loading the .soc file on the
FPGA. I put the "other pin's tree-state" option (so MAX processor
doesn't reload factory config), but the project doesn't work. I think
there are some problems on pin assignments, but I followed the pin
tables found on 'Nios II dev Reference Manual (May 2006)'. The board is
old, about end of 2004... Is this the problem in your opinion? Can you
tell me where I could find old specifications (here I haven't original
documentation) on the internet (I haven't found in altera site...)?
Or can I missing some important step? (like tree-state buffer for
unused pins that isn't showed clearly in documentation).

I don't use Nios processor, I need only FPGA for a fir filter using
Quartus II.

Any suggestions are welcome! :)

Thank you very much
Dario