Virtex-II Pro Platform FPGA : Assembling the modules

Hi, I am trying to do the partial reconfiguration. I almost came to the final step which is place and route of the logic of the completely expanded design. After using this command:

par -w top.ncd top_routed.ncd

I meet this error: FATAL_ERROR:Guide:basgitaskphyspr.c:372:1.28.20.3:286 - A previous module has placed the comp: Pim/myRegister/myRegister/PWR_VCC_0 on the same site: SLICE_X43Y159 where the current guide comp PWR_VCC_0 also needs to be placed.

Please tell me what happens and how to fix it.

Thank you so much for your time. Thang Nguyen

Hi Thang Nguyen,

are you using VCC-components in your bus-macros(*.nmc)? Don't include
VCC-Blocks in bus-macros.

Regards

Jens

THANG NGUYEN schrieb:

> Hi, I am trying to do the partial reconfiguration. I almost came to the final step which is place and route of the logic of the completely expanded design. After using this command:
>
> par -w top.ncd top_routed.ncd
>
> I meet this error: FATAL_ERROR:Guide:basgitaskphyspr.c:372:1.28.20.3:286 - A previous module has placed the comp: Pim/myRegister/myRegister/PWR_VCC_0 on the same site: SLICE_X43Y159 where the current guide comp PWR_VCC_0 also needs to be placed.
>
> Please tell me what happens and how to fix it.
> 
> Thank you so much for your time. Thang Nguyen

Thank Jens, Actually I use the bus macro bm_4b_v2p.nmc in the folder \bus_macros\angle_delimiter of the axemple xapp290 of Xilinx because I use the ML310 with the FPGA Virtex II Pro. As your recommend, should I recreate the bus macro?

Thank so much for your time. Thang Nguyen

Hi, As I know, there is not VCC-Blocks in the bus macro. Is this the problem about bus macro? Or the broblem of the module myRegister? Thanks Thang Nguyen

Hi Thang,

the xilinx bus marcos will be ok. I'm not sure about the software
you're using, but if doing partial reconfiguration, i would strongly
suggest to use the Early Access Partial Reconfiguration Patch for 8.1i.


http://www.xilinx.com/xlnx/xil_entry2.jsp?sMode=login&group=prealounge

See also the paper presented by xilinx on FPL06: "Enhanced
architectures, design methodologies and CAD tools for dynamic
reconfiguration of xilinx FPGAs"

Regards,

Jens

THANG NGUYEN schrieb:

> Hi, As I know, there is not VCC-Blocks in the bus macro. Is this the problem about bus macro? Or the broblem of the module myRegister? Thanks Thang Nguyen

Hi, I use the ISE 6.3i. I also try it with the ISE 8.2i in my University, but it doesn't work with the macro, I think so. This is the error message when I use 8.2i:

WARNING:Pds:119 - Attempted to load old format .nmc file "C:\THANG\CPR1\implementation\top_level_initial/bm_4b_v2p.nmc", but this format is no longer supported. EXCEPTION:Pds:Pds_PahFileConv.c:124:1.17 - Database conversion failed. FATAL_ERROR:NgdBuild:Portability/export/Port_Main.h:127:1.5.56.1 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate.

This project is really important to me. I start working on my master thesis, and this is my first step. Thank you for your answers.

Hi Thang,

the NMC/NCD format has changed between ISE6/7. There is a way to
convert the macros, but i would suggest to use the ones from the xilinx
website for PREAT8 flow. The Early Access Partial Reconfiguration Suite
contains basic busmacros, examples, and much more. It may also be
possible, if you, for whatever reason, not be able to use ISE8.1, to
use the old patch for partial reconfiguration, based on ISE6.3. A new
partial reconfiguration patch, based on ISE 8.2, should become
available soon.

Regards,

Jens

THANG NGUYEN schrieb:

> Hi, I use the ISE 6.3i. I also try it with the ISE 8.2i in my University, but it doesn't work with the macro, I think so. This is the error message when I use 8.2i:
>
> WARNING:Pds:119 - Attempted to load old format .nmc file "C:\THANG\CPR1\implementation\top_level_initial/bm_4b_v2p.nmc", but this format is no longer supported. EXCEPTION:Pds:Pds_PahFileConv.c:124:1.17 - Database conversion failed. FATAL_ERROR:NgdBuild:Portability/export/Port_Main.h:127:1.5.56.1 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate.
>
> This project is really important to me. I start working on my master thesis, and this is my first step. Thank you for your answers.

Hi,

"but i would suggest to use the ones from the xilinx website for PREAT8 flow. The Early Access Partial Reconfiguration Suite contains basic busmacros, examples, and much more. It may also be possible, if you, for whatever reason, not be able to use ISE8.1, to use the old patch for partial reconfiguration, based on ISE6.3. "

Could you tell me where I can find it? I try to search but I did not find the patch for ISE 6.3i. Thank you so much. Thang Nguyen

http://www.xilinx.com/support/prealounge/protected/archive.htm

Regards,

Jens


THANG NGUYEN schrieb:

> Hi,
>
> "but i would suggest to use the ones from the xilinx website for PREAT8 flow. The Early Access Partial Reconfiguration Suite contains basic busmacros, examples, and much more. It may also be possible, if you, for whatever reason, not be able to use ISE8.1, to use the old patch for partial reconfiguration, based on ISE6.3. "
>
> Could you tell me where I can find it? I try to search but I did not find the patch for ISE 6.3i. Thank you so much. Thang Nguyen

Hi Jens, Thank you for your patience answering my questions. Your help is really important with me. I am very appreciate your answers.

I installed the Service Pack 3 for ISE 6.3i. After that I rebuild the system again. And when I came to the command:

par -w top.ncd top_routed.ncd

I meet a new error:

Loading device database for application Par from file "..\Pim/myRegister/myRegister.ncd". "top" is an NCD, version 2.38, device xc2vp30, package ff896, speed -6 FATAL_ERROR:Guide:basgitaskphyspr.c:333:1.28.20.4:137 - Guide encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1 that does not have a driver or load within the module boundary. This problem may be caused by having a constant driving the input from outside the module boundary or because a driver or load comp did not meet the par-guiding criteria. The design will not be completely placed and routed by Par-Guide Process will terminate. To resolve this error, please consult the Answers Database and other online resources at <http://support.xilinx.com>. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at <http://support.xilinx.com>

Do I miss any package? Because I just found the SP3 for ISE 6.3i. The Early Access Partial Reconfiguration Suite is only support for ISE 8.1i, while I use ISE 6.3i.