Design of a programmable delay line

Hello,

For a future project I need to design a programmable delay line. The
specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no
PLLs left so I can't use a high-speed pipeline to design this. Note
that the delay should be fixed when temperature varies, this means that
I'll probably need some calibration.
I think that Xilinx uses something like this to delay the DQS signal in
the S3E DDR controller.
Has anybody got an idea how I should implement this?

best regards,
Dolphin

Dolphin schrieb:
> Hello,
> 
> For a future project I need to design a programmable delay line. The
> specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no

Why reinvent the wheel? Such delay lines are available off the shelf.

Regards
Falk

Falk Brunner schreef:

> Dolphin schrieb:
> > Hello,
> >
> > For a future project I need to design a programmable delay line. The
> > specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no
>
> Why reinvent the wheel? Such delay lines are available off the shelf.
>
> Regards
> Falk

These programmable delay lines are rather expensive.
Each IC counts for this design.

best regards,
Dolphin

Dolphin schrieb:

> These programmable delay lines are rather expensive.
> Each IC counts for this design.

Hmm, did you do a rough calculation of part cost versus design cost? 
Such a delay line in a FPGA is not done on a sunny weekend.
What quantities are required?

Regards
Falk

Falk,

This design is for a consumer product. It is for big quantities
(10K/year).
Each dollar counts.
Do you know cheap delay lines? I've checked the maxim parts but they
are rather expensive.

best regards,
Dolphin

>Do you know cheap delay lines? I've checked the maxim parts but they
>are rather expensive.

> specifications are: steps of +/- 1 ns, range of 0 to 8 ns.

PCB traces are about 6 inches per ns.


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Dolphin schrieb:
> Falk,
> 
> This design is for a consumer product. It is for big quantities
> (10K/year).
> Each dollar counts.
> Do you know cheap delay lines? I've checked the maxim parts but they
> are rather expensive.

Sorry, I don't.

Regards
Falk

Dolphin wrote:
> Hello,
> 
> For a future project I need to design a programmable delay line. The
> specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no
> PLLs left so I can't use a high-speed pipeline to design this. Note
> that the delay should be fixed when temperature varies, this means that
> I'll probably need some calibration.
> I think that Xilinx uses something like this to delay the DQS signal in
> the S3E DDR controller.
> Has anybody got an idea how I should implement this?
> 
> best regards,
> Dolphin
> 

Which FPGA?  If Virtex4, you can use the idelays which will give you 64 
steps of 75ps resolution, or you can use the io serializers.

What clocks do you have to work with?  Are the clk90 DCM outputs available?

Hi,

This is for a Cyclone II FPGA.

best regards,
dolphin

Ray Andraka schreef:

> Dolphin wrote:
> > Hello,
> >
> > For a future project I need to design a programmable delay line. The
> > specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no
> > PLLs left so I can't use a high-speed pipeline to design this. Note
> > that the delay should be fixed when temperature varies, this means that
> > I'll probably need some calibration.
> > I think that Xilinx uses something like this to delay the DQS signal in
> > the S3E DDR controller.
> > Has anybody got an idea how I should implement this?
> >
> > best regards,
> > Dolphin
> >
>
> Which FPGA?  If Virtex4, you can use the idelays which will give you 64
> steps of 75ps resolution, or you can use the io serializers.
>
> What clocks do you have to work with?  Are the clk90 DCM outputs available?

Dolphin wrote:
> Hello,
> 
> For a future project I need to design a programmable delay line. The
> specifications are: steps of +/- 1 ns, range of 0 to 8 ns. I have no
> PLLs left so I can't use a high-speed pipeline to design this. Note
> that the delay should be fixed when temperature varies, this means that
> I'll probably need some calibration.
> I think that Xilinx uses something like this to delay the DQS signal in
> the S3E DDR controller.
> Has anybody got an idea how I should implement this?
> 
> best regards,
> Dolphin

Overspecifying can kill the possible solutions.

Are you sure you need 1 ns steps?  Can n steps (n>=8) that can be shown 
through internal measurements to cover 8 ns be sufficient?  Can you 
handle some drift with temperature as long as you can adjust the taps 
when the change makes another tap more "ideal" for a fixed time?

With a CycloneII you probably have zero chance of a PVT-independent 
(process, voltage, tolerance) delay line or a delay line with explicit 
precision (e.g., 1.0 ns steps).

Can you look at other families?  The DQS circuitry you might recall 
could be from the Xilinx Virtex4 or the Lattice ECP2 family.  The 
Virtex-4 uses calibration, the ECP2 uses DLLs and neither covers the 8ns 
range.

External PCB traces from identical drivers to identical drivers might be 
your only hope, but it's real estate.

Good luck with your desires.